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What will happen for the histogram of the ADC if the last conversion is not done (Read 449 times)
Jacki_2016
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What will happen for the histogram of the ADC if the last conversion is not done
Aug 02nd, 2022, 6:12am
 
Hello,

   My question is if the SARADC doesn't have enough time to complete the last bit conversion, what will the linearity be affected? What does the histogram look like? Could anybody give me some hints or links?
   Thank you.
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smlogan
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Re: What will happen for the histogram of the ADC if the last conversion is not done
Reply #1 - Jan 15th, 2023, 10:34am
 
Dear Jacki_2016,

If I understand your question correctly, I think what you are asking is what are the consequences if an N bit ideal A/D has an accuracy limitation such that it is accurate to N - 1 bit.

Do you know if the error mechanism results in an error with a specific PDF or bias or are the errors truly random? If the probability of an error is  random, then the linearity of your N bit A/D will be no better than that for a (N-1) bit A/D. The histogram in that case, if I understand what your notion of a histogram is, will show it to be a N-1 bit quantizer in lieu of an N bit quantizer.

Does this help Jacki_2016, or did I misunderstand your question?
Shawn
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Shawn
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