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Feb 26th, 2024, 3:42am
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Intergtared PGA design problems for delta sigma modulator (Read 301 times)
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Intergtared PGA design problems for delta sigma modulator
Jan 15th, 2023, 7:21pm
A PGA is required for a high precision DC signal sensing DSM ADC, with function of providing 1~128 signal gain, rail-to-rail input/output, buffering the ADC's SC sampling circuits. Other requirements are also critical: high input impendace, low noise/aliasing, low offset, low power, low INL.

There are generally 2 kinds of strcuture:
1) Resitive Feedback using two OPAs, Buffers are required to driving S/H stage.
2) Capacitive coupled PGA using 1 OPA, input precharge buffers are required to provide high input impendance.

Main challenges:
1) Driving capacibility is conflict with low alasing, anti-aliasing filter is requried before ADC S/H stage, but this will degrade the settling.
2) Varieties of dynamic techniques are used to improve settling without bringing noise problem. e.g. precharge, dynamic filter. BUT the switch's glitch become another serious problem.
3) Even I have solved all problems listed below, the power consumption is relatively high compared with industry benchmark.

I read many IA's papers (Huijsing, e.t.), but these IAs are usually designed for monolithic chip, usually a very large decoupling cap is conencted at the output.

Could anyone help point out any mistake of my understanding above? or provide any inspiration, materials about integrated PGA? Thank you very much!
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« Last Edit: Jan 16th, 2023, 4:16pm by designer_ring »  
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