Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
100 MHz oscillator on ~0.18um CMOS	AnalogDE	0	13	Apr 1^st, 2020, 9:57pm By: AnalogDE
Split Array Capacitive DAC	Bean Nakamura	4	108	Mar 17^th, 2020, 8:12pm By: Bean Nakamura
Switching power in cap	mks	3	112	Mar 12^th, 2020, 4:51am By: rajasekhar
pnoise/jitter and pnoise/time average discrepancy with Cadence Spectre	threepwood	0	97	Feb 13^th, 2020, 10:39am By: threepwood
VCO	MILIND BHANDARI	2	270	Jan 12^th, 2020, 11:55pm By: subtr
DAC noise analysis?	Jacki	2	235	Jan 6^th, 2020, 9:08am By: neoflash
Scaling of Sampling clock in CT-SDM ADC	neoflash	0	89	Jan 2^nd, 2020, 4:23pm By: neoflash
Moved: STB vs AC analysis - different result - Started by: Andrew94 This Topic has been moved to Circuit Simulators by Ken Kundert
How to speed up RJ sim for DLL including Regulator	aks	4	256	Dec 9^th, 2019, 2:18am By: aks
Ring Oscillator Pre vs. Post Layout Frequency Shift	melvin1109	2	230	Dec 7^th, 2019, 1:58pm By: Maks
Noise sims for switched capacitor amplifiers	vm511	0	93	Nov 25^th, 2019, 12:10pm By: vm511
comparator offset voltage simulation veriloga model	Hesham	6	227	Nov 16^th, 2019, 3:19am By: Hesham
anti-aliasing filter for ADCs	polyam	1	281	Oct 4^th, 2019, 7:28am By: Andrew Beckett
Poles and zeros in all pass filter.	Jacki	5	142	Sep 9^th, 2019, 5:47am By: Jacki
MOSFET OP parameters for a small-signal model	IBurmistrov	1	205	Sep 8^th, 2019, 10:48pm By: IBurmistrov
Output-referred Offset in switched capacitor amplifier	vm511	0	159	Sep 4^th, 2019, 2:12pm By: vm511
bandgap couldn't lock to Vref.	Jacki	8	673	Aug 13^th, 2019, 6:48am By: Jacki
Symmetric zeros, does it matter?	Jacki	3	325	Aug 13^th, 2019, 2:06am By: Horror Vacui
Ring Oscillator (Tuned Load stage) « Pages 1 2 »	cktdesigner	15	252	Aug 12^th, 2019, 7:17am By: kumar.g
OTA Closed loop Simulation	kingdarius	2	107	Aug 12^th, 2019, 6:44am By: Horror Vacui

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