The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 1:55pm
Pages: 1
Send Topic Print
any analysis paper on stack mos array? (Read 75 times)
neoflash
Community Fellow
*****
Offline

Mixed-Signal
Designer

Posts: 397

any analysis paper on stack mos array?
Oct 05th, 2022, 9:08pm
 
Like how to calculate the stack mos gm, gds, vdsat and etc?

Thanks!
Back to top
 
 
View Profile   IP Logged
dpalma
New Member
*
Offline



Posts: 1

Re: any analysis paper on stack mos array?
Reply #1 - Jan 24th, 2023, 2:43am
 
Also interested in this topic. A drop here a reference I found helpful

D. Lee and J. Han, «Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology», 18th International SoC Design Conference (ISOCC), 2021. doi: 10.1109/ISOCC53507.2021.9613881.
Back to top
 
 
View Profile   IP Logged
davidshw
Junior Member
**
Offline



Posts: 12
China
Re: any analysis paper on stack mos array?
Reply #2 - Feb 5th, 2023, 7:49pm
 
This paper may be helpful.

C. Galup-Montoro, M. C. Schneider, and I. J. Loss, ‘Series-parallel association of FET’s for high gain and high frequency applications’, IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1094–1101, 1994.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.