Designer’s Guide Community :: Forum

Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.

Apr 30^th, 2025, 2:59am

	HomeHelpSearchLoginRegisterPM to admin

The Designer's Guide Community Forum › Design › Analog Design › any analysis paper on stack mos array?

‹ Previous topic | Next topic ›

Pages: 1

Send Topic

Print

any analysis paper on stack mos array? (Read 579 times)

neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	any analysis paper on stack mos array? Oct 05^th, 2022, 9:08pm Like how to calculate the stack mos gm, gds, vdsat and etc? Thanks!
Back to top	IP Logged

dpalma New Member Offline Posts: 1	Re: any analysis paper on stack mos array? Reply #1 - Jan 24^th, 2023, 2:43am Also interested in this topic. A drop here a reference I found helpful D. Lee and J. Han, �Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology�, 18th International SoC Design Conference (ISOCC), 2021. doi: 10.1109/ISOCC53507.2021.9613881.
Back to top	IP Logged

davidshw Junior Member Offline Posts: 12 China	Re: any analysis paper on stack mos array? Reply #2 - Feb 5^th, 2023, 7:49pm This paper may be helpful. C. Galup-Montoro, M. C. Schneider, and I. J. Loss, �Series-parallel association of FET�s for high gain and high frequency applications�, IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1094�1101, 1994.
Back to top	IP Logged

Pages: 1

Send Topic

Print

‹ Previous topic | Next topic ›

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.