What's the timing window to update dual-modulus divider divider ratio control?

Any advantage of using both N and P MOS in an LNA?

source voltage

Basic question on transmission line

Simulate odd mode/even mode impedance of coupler using S param sim

Checking undesired substrate mode in transmission line.

Moved: Cadence Layout Cannot Show PDK Instance Graph - Started by: ovicovic
This Topic has been moved to Entry Tools by Ken Kundert

Moved: Cap extraction of an IC  PAD - Started by: vlsi_design
This Topic has been moved to Physical Verification, Extraction and Analysis by Ken Kundert

Does metal (copper, aluminum) shielding really help inductors in ICs?

NTF of frac-N PLL divider quantization noise

LNA tail current biasing

[Help] SpectreRF pnoise simulation: sampled output noise of a chopping amplifer

Noise Figure in switched cap, with Pnoise

QPSS setup for mixer

N-Path Mixer NF

N-path, Cadence virtuoso, LSSP

Loaded quality factor of voltage control oscillator

Questions about class-F and Inverse class-F RF power amplifiers

How to ensure the pll loop stability with VCO gain variation?

ABCD parameters matrix of unsymmetric coupled lines