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Aug 14th, 2022, 2:55am
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Basic question on transmission line (Read 137 times)
vlsi_design
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Basic question on transmission line
Mar 29th, 2022, 7:11am
 
Hi,
T lines no matter how long they are, if properly terminated with ZL=Z0=R, always presents a resistive load and no capacitive load. Instead if I use a long trace of line of comparable dimension I get a huge capacitor with the substrate (say). Is there an intuitive way to understand this? or the best way is to rely on theoretical formula of Zin = f(Z0,ZL,tan(beta*l)) where once we substitute Z0=ZL, we see pure resistive input impedance?
How the huge cap magically disappears?
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Horror Vacui
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Re: Basic question on transmission line
Reply #1 - Jul 26th, 2022, 4:43am
 
Aren't you looking at low frequencies? What is the electrical length of the structure? At DC every t-line is a cap. (beta has a frequency dependence: at f=0 beta goes to 0. I prefer the substitution: beta*l=2*pi*{electrical length}, because it makes things in the argument of the tangent easier to grasp)
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