Hi, the following code is generating the error:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity program_counter is
   port (
       clk, en_A, ld, inc, reset: in STD_LOGIC;
       aBus: out STD_LOGIC_VECTOR(15 downto 0);
       dBus: in STD_LOGIC_VECTOR(15 downto 0)
   );
end program_counter;
architecture pcArch of program_counter is
signal pcReg : STD_LOGIC_VECTOR(15 downto 0);
begin
 process(clk) begin
       if clk'event and clk = '1' then
             if reset = '1' then
                   pcReg <= x"0000";
             elsif ld = '1' then
                   pcReg <= dBus;
             elsif inc = '1' then
           pcReg <= pcReg + x"0001";
             end if;
       end if;
 end process;
 aBus <= pcReg when en_A = '1' else "ZZZZZZZZZZZZZZZZ";
end pcArch;

Specifically on the line:

pcReg <= pcReg + x"0001";

The error is:

(ARCHITECTURE pcarch OF ENTITY program_counter) : Error : Type mismatch

Please help with a fix.

I don't think so Geoffrey -  VHDL is a case insensitive language... I just checked in a book I have and it says "The base specifier can be in uppercase or lowercase".

Note that the module above when compiled in ncvhdl gives:

ncvhdl: 15.20-s028: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
                  pcReg <= x"0000";
                                 |
ncvhdl_p: *E,EXPTYP (forum2.vhd,17|34): expecting an expression of type STD_LOGIC_VECTOR 87[8.3] 93[8.4].
          pcReg <= pcReg + x"0001";
                         |
ncvhdl_p: *E,BITOPR (forum2.vhd,21|26): This feature is allowed only in 93[13.7].

However, if I compile with -v93 or -v200x then it compiles with no problem.

Regards,

Andrew.