Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Minor glitches in nonlinear magnetics paper	Geoffrey_Coram	10	3184	Jan 25^th, 2022, 2:22pm By: Geoffrey_Coram
Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in	bernd2700	14	653	Jan 11^th, 2022, 7:36am By: bernd2700
Output-referred kT/C noise combined with T&H and with sw.cap integrator	bernd2700	0	115	Nov 4^th, 2021, 2:11am By: bernd2700
Machine-Learning-based-Behavioral Modelling	rhanna	0	290	Apr 19^th, 2021, 6:33am By: rhanna
Machine-Learning-based-Behavioral Modelling	rhanna	0	177	Apr 19^th, 2021, 6:30am By: rhanna
Noise: Track & Hold: Theory <=> Sim.: Fits for f3dB >> fs but do	bernd2700	6	409	Apr 8^th, 2021, 8:20am By: bernd2700
Hidden states in digital converter control blocks	Nicolae Adrian	3	413	Mar 24^th, 2021, 7:39pm By: Ken Kundert
Addressing Parasitic Extraction on Top-level Routing	rhanna	3	529	Nov 14^th, 2020, 3:28pm By: Maks
Simple Inductor model in SystemVerilog using Cadence EEnet	sanforyou	2	452	Oct 29^th, 2020, 7:44am By: Geoffrey_Coram
Oscillator Modelling by Dipolar Method	Vitor	6	627	Sep 30^th, 2020, 3:13pm By: Ken Kundert
VCO Phase Noise 40dB/dec instead of 20dB/dec in PNoise	Hudson	2	557	Jul 9^th, 2020, 12:43pm By: Hudson
MUX Element in AnalogLib or ahdlLib in Cadence for Time Interleaved ADC	repah	1	480	May 12^th, 2020, 12:26am By: Andrew Beckett
Time Interleaved ADC	repah	0	333	May 7^th, 2020, 2:15pm By: repah
how to deal with segmentation fault in veriloga simulation	Bisharp	5	769	Mar 8^th, 2020, 4:03am By: Bisharp
The problem of bus width of output terminal	Bisharp	4	625	Mar 5^th, 2020, 7:03am By: Andrew Beckett
Injection locked oscillator model	polyam	0	443	Nov 20^th, 2019, 5:43am By: polyam
What is wrong with this comparator verilog-A model	spunky	4	986	Aug 30^th, 2019, 10:32am By: Hesham
veriloga driver model « Pages 1 2 »	michdundee78	20	2038	Jul 31^st, 2019, 7:17pm By: hafiz2431
Model optocoupler NSL-32SR3	Leonardo	1	479	Jul 12^th, 2019, 7:24am By: Geoffrey_Coram
VerilogA-instantiation of array of modules using looping structure	Anish	2	981	May 2^nd, 2019, 10:09am By: Anish

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