Designer’s Guide Community

Pages: 1 2 3 ... 16

Subject	Started by	Replies	Views	Last post
VCO Phase Noise 40dB/dec instead of 20dB/dec in PNoise	Hudson	2	121	Jul 9^th, 2020, 12:43pm By: Hudson
MUX Element in AnalogLib or ahdlLib in Cadence for Time Interleaved ADC	repah	1	149	May 12^th, 2020, 12:26am By: Andrew Beckett
Time Interleaved ADC	repah	0	63	May 7^th, 2020, 2:15pm By: repah
how to deal with segmentation fault in veriloga simulation	Bisharp	5	188	Mar 8^th, 2020, 4:03am By: Bisharp
The problem of bus width of output terminal	Bisharp	4	149	Mar 5^th, 2020, 7:03am By: Andrew Beckett
Injection locked oscillator model	polyam	0	186	Nov 20^th, 2019, 5:43am By: polyam
What is wrong with this comparator verilog-A model	spunky	4	440	Aug 30^th, 2019, 10:32am By: Hesham
veriloga driver model « Pages 1 2 »	michdundee78	20	493	Jul 31^st, 2019, 7:17pm By: hafiz2431
Model optocoupler NSL-32SR3	Leonardo	1	200	Jul 12^th, 2019, 7:24am By: Geoffrey_Coram
VerilogA-instantiation of array of modules using looping structure	Anish	2	521	May 2^nd, 2019, 10:09am By: Anish
VCO VerilogA hidden state	Marios	5	670	Apr 6^th, 2019, 12:23am By: Ken Kundert
laplace_nd and Algebra and VerilogA	kevinvinv	0	245	Mar 15^th, 2019, 12:31pm By: kevinvinv
Passing in a bias point for a verilogA model	kevinvinv	1	294	Mar 14^th, 2019, 2:58pm By: kevinvinv
Checking list for modelling as real number	nasser786	0	400	Jan 30^th, 2019, 11:25pm By: nasser786
Ferroelectric Capacitor model using verilog-a	aguntuk	3	829	Jan 28^th, 2019, 3:30pm By: Ken Kundert
Verilog-A : Behavioral model analyzer/optimizer	AS	2	766	Dec 7^th, 2018, 4:28am By: Andrew Beckett
verilog-a code delay and pulse width generation.	openloop	1	760	Oct 27^th, 2018, 12:17am By: Ken Kundert
veriloga counter_	moreed	1	1033	Jul 7^th, 2018, 1:15am By: Ken Kundert
Verilo A model	ouijdane	2	1294	Jul 6^th, 2018, 9:00am By: Frank Wiedmann
VerilogA model for Current Monitoring	sanforyou	2	1642	May 30^th, 2018, 9:31am By: sanforyou

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