Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Simple Inductor model in SystemVerilog using Cadence EEnet	sanforyou	1	63	Oct 2^nd, 2020, 12:06pm By: sanforyou
Oscillator Modelling by Dipolar Method	Vitor	6	175	Sep 30^th, 2020, 3:13pm By: Ken Kundert
VCO Phase Noise 40dB/dec instead of 20dB/dec in PNoise	Hudson	2	229	Jul 9^th, 2020, 12:43pm By: Hudson
MUX Element in AnalogLib or ahdlLib in Cadence for Time Interleaved ADC	repah	1	201	May 12^th, 2020, 12:26am By: Andrew Beckett
Time Interleaved ADC	repah	0	102	May 7^th, 2020, 2:15pm By: repah
how to deal with segmentation fault in veriloga simulation	Bisharp	5	302	Mar 8^th, 2020, 4:03am By: Bisharp
The problem of bus width of output terminal	Bisharp	4	256	Mar 5^th, 2020, 7:03am By: Andrew Beckett
Injection locked oscillator model	polyam	0	241	Nov 20^th, 2019, 5:43am By: polyam
What is wrong with this comparator verilog-A model	spunky	4	535	Aug 30^th, 2019, 10:32am By: Hesham
veriloga driver model « Pages 1 2 »	michdundee78	20	830	Jul 31^st, 2019, 7:17pm By: hafiz2431
Model optocoupler NSL-32SR3	Leonardo	1	263	Jul 12^th, 2019, 7:24am By: Geoffrey_Coram
VerilogA-instantiation of array of modules using looping structure	Anish	2	606	May 2^nd, 2019, 10:09am By: Anish
VCO VerilogA hidden state	Marios	5	781	Apr 6^th, 2019, 12:23am By: Ken Kundert
laplace_nd and Algebra and VerilogA	kevinvinv	0	285	Mar 15^th, 2019, 12:31pm By: kevinvinv
Passing in a bias point for a verilogA model	kevinvinv	1	350	Mar 14^th, 2019, 2:58pm By: kevinvinv
Checking list for modelling as real number	nasser786	0	446	Jan 30^th, 2019, 11:25pm By: nasser786
Ferroelectric Capacitor model using verilog-a	aguntuk	3	939	Jan 28^th, 2019, 3:30pm By: Ken Kundert
Verilog-A : Behavioral model analyzer/optimizer	AS	2	866	Dec 7^th, 2018, 4:28am By: Andrew Beckett
verilog-a code delay and pulse width generation.	openloop	1	828	Oct 27^th, 2018, 12:17am By: Ken Kundert
veriloga counter_	moreed	1	1120	Jul 7^th, 2018, 1:15am By: Ken Kundert

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