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What is wrong with this comparator verilog-A model (Read 109 times)
spunky
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What is wrong with this comparator verilog-A model
Aug 26th, 2019, 4:25pm
 
I have built a Verilog-A comparator model as shown in the attached picture.

Basically it is just a linear gain stage to process the input voltage delta and then output either high or low with delay.

I am noticing the comparator can give wrong state at output, i.e., the output stuck at low/high when the input delta is obviously positive/negative, especially when one of the input signal is chattering around another. And after that, the output will stuck.

Another thing I have noticed is changing the magnitude of its linear gain sometimes help, but not always.

I am very frustrated about it currently and need comments or suggestions on what the issue could be and how to improve my code for behavior modeling of comparators.

Thanks!
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2019-08-26_16-15-49.png
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spunky
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Re: What is wrong with this comparator verilog-A model
Reply #1 - Aug 26th, 2019, 4:28pm
 
Not sure how to attach the 2nd picture showing the simulated results.
But here it is.
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2019-08-26_16-20-49.png
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Ken Kundert
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Re: What is wrong with this comparator verilog-A model
Reply #2 - Aug 26th, 2019, 6:50pm
 
Seems like a lot of complexity for a comparator model. I recommend that you start simple, get that working, and then only add what you really need. A good starting point would be the Verilog-A comparator on the Verilog-AMS page.

-Ken
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Geoffrey_Coram
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Re: What is wrong with this comparator verilog-A model
Reply #3 - Aug 28th, 2019, 7:09am
 
Rather than two cross statements, trying to catch it as it goes one way or the other, I'd use one cross statement for timestep control:
Code:
    @(cross((V(inp, inm) - vthres/comp_gain)))
	  ; // null statement 



and then have a plain if statement to set out_val and del:
Code:
    if (V(inp, inm) > vthres/comp_gain) begin
	  out_val = 1;
	  del = comp_delay_r;
    end else begin
	  out_val = 0;
	  del = comp_delay_f;
    end 



I'd have to read up on what the LRM says happens if you happen to hit the threshold exactly: is this a cross event? in which direction? And then I'd have to wonder if the simulator implemented it correctly.
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Hesham
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Re: What is wrong with this comparator verilog-A model
Reply #4 - Aug 30th, 2019, 10:32am
 
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