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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> What is wrong with this comparator verilog-A model https://designers-guide.org/forum/YaBB.pl?num=1566861946 Message started by spunky on Aug 26th, 2019, 4:25pm |
Title: What is wrong with this comparator verilog-A model Post by spunky on Aug 26th, 2019, 4:25pm I have built a Verilog-A comparator model as shown in the attached picture. Basically it is just a linear gain stage to process the input voltage delta and then output either high or low with delay. I am noticing the comparator can give wrong state at output, i.e., the output stuck at low/high when the input delta is obviously positive/negative, especially when one of the input signal is chattering around another. And after that, the output will stuck. Another thing I have noticed is changing the magnitude of its linear gain sometimes help, but not always. I am very frustrated about it currently and need comments or suggestions on what the issue could be and how to improve my code for behavior modeling of comparators. Thanks! |
Title: Re: What is wrong with this comparator verilog-A model Post by spunky on Aug 26th, 2019, 4:28pm Not sure how to attach the 2nd picture showing the simulated results. But here it is. |
Title: Re: What is wrong with this comparator verilog-A model Post by Ken Kundert on Aug 26th, 2019, 6:50pm Seems like a lot of complexity for a comparator model. I recommend that you start simple, get that working, and then only add what you really need. A good starting point would be the Verilog-A comparator on the Verilog-AMS page. -Ken |
Title: Re: What is wrong with this comparator verilog-A model Post by Geoffrey_Coram on Aug 28th, 2019, 7:09am Rather than two cross statements, trying to catch it as it goes one way or the other, I'd use one cross statement for timestep control: Code:
and then have a plain if statement to set out_val and del: Code:
I'd have to read up on what the LRM says happens if you happen to hit the threshold exactly: is this a cross event? in which direction? And then I'd have to wonder if the simulator implemented it correctly. |
Title: Re: What is wrong with this comparator verilog-A model Post by Hesham on Aug 30th, 2019, 10:32am Hi Spunky Please check this https://designers-guide.org/forum/YaBB.pl?num=1562183339/3#3 |
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