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Aug 22nd, 2019, 3:37pm
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veriloga driver model (Read 326 times)
Ken Kundert
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Re: veriloga driver model
Reply #15 - Jul 30th, 2019, 3:48pm
 
Yeah, your model has some relatively obvious mistakes. Perhaps they would be easier to see if you removed the dead code.  Also, you did not follow instructions very well.

-Ken
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hafiz2431
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Re: veriloga driver model
Reply #16 - Jul 30th, 2019, 7:04pm
 
OK, here it is:

`include "constants.vams"
`include "disciplines.vams"

module drv_ideal(A, Y, vcc);
output Y;
electrical Y;
input A,vcc;
electrical A,vcc;

// INSTANCE PARAMETERS:
parameter real vhi = 0.8;              
parameter real vlo = 0  ;
parameter real vth = 0.5*(vhi+vlo) ;
parameter real tr = 15p;
parameter real tf = 15p;
parameter real tdel =0;
parameter real rpuon =35;
parameter real rpdon =35;
parameter real roff =10M;

// LOCAL VARIABLES:
real vy,rpu,rpd;      

analog begin
   @ (cross(V(A) - vth, 0) )
        vy =  (V(A) > vth);
       
     
      if (V(A) > vth)
           vy = vhi;
     else
           vy = vlo;
     
       
       rpu = transition(vy ? rpuon : roff ,tdel, tr,tf);
       I(vcc,Y) <+ V(vcc,Y)/rpu;

       rpd = transition(!vy ? rpdon : roff ,tdel, tr,tf);
       I(Y) <+ V(Y)/rpd;
     
end

endmodule
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Geoffrey_Coram
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Re: veriloga driver model
Reply #17 - Jul 31st, 2019, 6:13am
 
You allow vlo to take any value:

parameter real vlo = 0  ;

but your transition calls assume that vy == 0 means the driver is off:

      rpu = transition(vy ? rpuon : roff ,tdel, tr,tf);

What would happen if vlo = 1 (and vhi = 2)? Or if vlo = -1 and vhi = +1?
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hafiz2431
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Re: veriloga driver model
Reply #18 - Jul 31st, 2019, 8:57am
 
Yes, this issue needs to be resolved as well, but before that, would you please assist to figure out why the first 3 pulses at drv-resp-2.jpg are not going to 0?
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Ken Kundert
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Re: veriloga driver model
Reply #19 - Jul 31st, 2019, 11:51am
 
We cannot really tell you why your simulations are failing without having all the information. However, rather than providing us with the circuit and all the waveforms it would be better if you debugged the situation yourself. I recommend you thinking about the value of vy ? rpuon and !vy. Here you are treating vy, a real number, as a boolean. It is logically false if its value is 0.000000000000000000, and true otherwise. Is that really the way you want to write this model?

Given that you are clearly struggling, here are a few issues with your model:
Code:
@(cross(V(A) - vth, 0) )
    vy =  (V(A) > vth); 


Why are you computing vy here. You immediately overwrite with the next statement.

The next problem is here:
Code:
if (V(A) > vth)
    vy = vhi;
else
    vy = vlo; 


Why are you setting vy to vhi and vlo. vhi and vlo no longer have any meaning in this model, and the fact that you are using them leads to the problem Geoffrey is pointing out.

Perhaps you should replace the above code with the following:
Code:
@(cross(V(A) - vth, 0) )
    ;
vy =  (V(A) > vth); 



And while I am at it, why do you use vy as the name of your variable. The value is not a voltage, and y is meaningless. This poor choice of names is contributing to your problems. Perhaps you should use a name like on. It is very descriptive of both the meaning and the type of the value.

-Ken
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hafiz2431
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Re: veriloga driver model
Reply #20 - Jul 31st, 2019, 7:17pm
 
Thanks for the hints. I'll try to debug the issues.
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