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 veriloga driver model (Read 4592 times)
 michdundee78 New Member Offline Posts: 2 veriloga driver model Jun 22nd, 2019, 3:09am   Hi all,can someone help me on writing a veriloga driver model (ron, roff, delay) please?thx in advanceBR,mich Back to top IP Logged
 Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley Re: veriloga driver model Reply #1 - Jun 22nd, 2019, 4:36pm   Doesn't really work like that here. You generally have to make an effort first by proposing something, and then we can help you by answering your questions.-Ken Back to top IP Logged
 hafiz2431 New Member Offline Posts: 8 Re: veriloga driver model Reply #2 - Jul 25th, 2019, 3:57am   Hi,You can try the following code:`include "constants.vams"`include "disciplines.vams"module drv_ideal(A, Y, vcc);output Y;electrical Y;input A,vcc;electrical A,vcc;// INSTANCE PARAMETERS:parameter real vhi = 0.8;              parameter real vlo = 0  ; parameter real vth = 0.5*(vhi+vlo) ; parameter real tr = 1p; parameter real tf = 1p; parameter real tdel =1p; parameter real rpuon =35;parameter real rpdon =35;parameter real roff =10M;// LOCAL VARIABLES:real vy,rpu,rpd;       integer y;     analog begin           y =  (V(A) > vth);         vy = y ? vhi : vlo;            V(Y) <+ transition( vy, tdel, tr, tf);                rpu = transition(V(A)>vth ? rpuon : roff ,tdel, tr,tf);        I(vcc,Y) <+ V(vcc,Y)/rpu;        rpd = transition(V(A)
 Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA Re: veriloga driver model Reply #3 - Jul 25th, 2019, 5:08am   Hi, hafiz2431 -Your code probably not doing what you intended. You need to look at the rules of value retention in Verilog-A, because you are contributing to both the potential:    V(Y) <+ transition( vy, tdel, tr, tf);and flow:       I(Y) <+ V(Y)/rpd;of the same branch between Y and ground. The rules say that the V contribution will be discarded because of the subsequent I contribution. Back to top If at first you do succeed, STOP, raise your standards, and stop wasting your time.   IP Logged
 Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley Re: veriloga driver model Reply #4 - Jul 25th, 2019, 4:01pm   Also you need a cross function to resolve the threshold crossings in the input voltage. Back to top IP Logged
 hafiz2431 New Member Offline Posts: 8 Re: veriloga driver model Reply #5 - Jul 25th, 2019, 8:09pm   Hi Ken and Geoffrey,Thanks for your response. I'm not very familiar with Verilog-A. I can just write some simple codes. Actually, I tried to address the issue raised by michdundee78. As for the code, I could see the response at Y after a 'tdel' amount of delay from A. Moreover, I found pull-up and pull-down current at node Y equal to [V(vcc)-V(Y)]/rpuon and V(Y)/rpdon, respectively.  This served my purpose apparently but of course, I'd appreciate if you suggest some modifications. Back to top IP Logged
 Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley Re: veriloga driver model Reply #6 - Jul 25th, 2019, 9:36pm   You need a cross function to resolve the threshold crossings in the input voltage. Back to top IP Logged
 hafiz2431 New Member Offline Posts: 8 Re: veriloga driver model Reply #7 - Jul 29th, 2019, 3:23am   Hi Ken,I added a cross function and it now looks like:`include "constants.vams"`include "disciplines.vams"module drv_ideal(A, Y, vcc);output Y;electrical Y;input A,vcc;electrical A,vcc;// INSTANCE PARAMETERS:parameter real vhi = 0.8;              parameter real vlo = 0  ; parameter real vth = 0.5*(vhi+vlo) ; parameter real tr = 1p; parameter real tf = 1p; parameter real tdel =30p; parameter real rpuon =35;parameter real rpdon =35;parameter real roff =10M;// LOCAL VARIABLES:real vy,rpu,rpd;       integer y;     analog begin    @ (cross(V(A) - vth, 0) )         y =  (V(A) > vth);         vy = y ? vhi : vlo;            V(Y) <+ transition( vy, tdel, tr, tf);                rpu = transition(V(A)>vth ? rpuon : roff ,tdel, tr,tf);        I(vcc,Y) <+ V(vcc,Y)/rpu;        rpd = transition(V(A) high, a current =(0.8-0.4)/35 =11.4 mA will flow at a delay of 30 ps from Vs1 to Vs2. When in=> low, Vs2 will source 11.4 mA to ground. Back to top IP Logged
 Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA Re: veriloga driver model Reply #8 - Jul 29th, 2019, 6:05am   In small/short simulations, you may not notice a difference. If you ask the simulator to run a very long simulation, it may decide to take much larger timesteps, and it could step over a whole cycle and not notice that it was skipped. Back to top If at first you do succeed, STOP, raise your standards, and stop wasting your time.   IP Logged
 Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA Re: veriloga driver model Reply #9 - Jul 29th, 2019, 6:06am   If you comment out this line:  V(Y) <+ transition( vy, tdel, tr, tf);does the result change at all? Back to top If at first you do succeed, STOP, raise your standards, and stop wasting your time.   IP Logged
 Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley Re: veriloga driver model Reply #10 - Jul 29th, 2019, 10:45am   As Geoffrey says, the cross function controls the time point selection, so to see the difference you would need to look at the time point placement. Geoffrey mentioned that in long simulations you can miss entire output pulses, but if you control your time steps that is unlikely to happen, and if it does a cross function won't help. Instead the cross function helps by accurately resolving the time of the crossing. Without it the time of the output transition can be off by a large amount. An artificial jitter of 10-20% of the pulse width is not uncommon.Your use of cross has the 'start up' problem. The start-up problem results in the output being wrong at the beginning of the simulation. It only corrects itself after the first input transition. Instead, I recommend that you put the if statement outside the cross function ... Code:```@(cross(V(A) - vth, 0))     ; if (V(A) > vth)     vy = vhi; else     vy = vlo; ```Geoffrey is also trying to call attention to another very odd aspect of this model.  You are driving the output with a voltage source and also driving it with pull up and pull down resistors. The resistors would have no effect on the output voltage, instead they only affect the current in the supply and ground.-Ken Back to top « Last Edit: Jul 30th, 2019, 3:45pm by Ken Kundert »     IP Logged
 Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley Re: veriloga driver model Reply #11 - Jul 29th, 2019, 11:06am   For simulation efficiency, it is better to set tdel to 0 and make tr and tf as large as practical. So unless there is some reason to use a nonzero tdel or small tr and tf, you should not.I mention this because people often try to make their models needlessly more accurate without realizing that they are paying a price in simulation speed.-Ken Back to top IP Logged
 hafiz2431 New Member Offline Posts: 8 Re: veriloga driver model Reply #12 - Jul 30th, 2019, 12:51am   Thanks, Ken and Geoffrey for your valuable inputs. I appreciate that.How do you think about the code now:`include "constants.vams"`include "disciplines.vams"module drv_ideal(A, Y, vcc);output Y;electrical Y;input A,vcc;electrical A,vcc;// INSTANCE PARAMETERS:parameter real vhi = 0.8;              parameter real vlo = 0  ; parameter real vth = 0.5*(vhi+vlo) ; parameter real tr = 15p; parameter real tf = 15p; parameter real tdel =0; parameter real rpuon =35;parameter real rpdon =35;parameter real roff =10M;// LOCAL VARIABLES:real vy,rpu,rpd;       //integer y;     analog begin    @ (cross(V(A) - vth, 0) )         vy =  (V(A) > vth);        // vy = y ? vhi : vlo;             if (V(A) > vth)            vy = vhi;      else            vy = vlo;      // V(Y) <+ transition( vy, tdel, tr, tf);                //rpu = transition(V(A)>vth ? rpuon : roff ,tdel, tr,tf);        rpu = transition(vy ? rpuon : roff ,tdel, tr,tf);        I(vcc,Y) <+ V(vcc,Y)/rpu;        // rpd = transition(V(A)
 Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley Re: veriloga driver model Reply #13 - Jul 30th, 2019, 6:52am   Have you tried it? How does it work?-Ken Back to top IP Logged
 hafiz2431 New Member Offline Posts: 8 Re: veriloga driver model Reply #14 - Jul 30th, 2019, 9:12am   Yes, I tried to drive an extracted model of a transmission line. In=> input to the buffer, tx_pad<0> => output of the buffer driving the transmission line. The low level of the first 3 pulses are not zero but some other values. It's also due to initialization problem or else? Back to top IP Logged
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