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The problem of bus width of output terminal (Read 858 times)

Bisharp Junior Member Offline newbie Posts: 10 China	The problem of bus width of output terminal Mar 02^nd, 2020, 7:42pm For example, in these code written by Ken. the output has a bus width of 8. But when I create the symbol of this va view, the out<-1:0> will lead to an error... it seems the bits in the code is read as 0.. how can i create a editable bus width of terminal in symbol..
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Ken Kundert Global Moderator Offline Posts: 2358 Silicon Valley	Re: The problem of bus width of output terminal Reply #1 - Mar 2^nd, 2020, 9:42pm In some of my examples I made the bus width a parameters. That works in Verilog but not in the Cadence design environment. Make sure the bus width is given as a literal constant, ex: 8 -Ken
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Bisharp Junior Member Offline newbie Posts: 10 China	Re: The problem of bus width of output terminal Reply #2 - Mar 3^rd, 2020, 1:32am Thank you Ken I tried the definition like "`define BITS 8",and use "`BITS" in the code, it passed in the cadence environment. However, the bus width can 't edit, because the symbol is fixed. (I guess maybe the skill language can do something, i will try. sorry for my poor english
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Ken Kundert Global Moderator Offline Posts: 2358 Silicon Valley	Re: The problem of bus width of output terminal Reply #3 - Mar 3^rd, 2020, 3:03pm Correct, the bus width in symbols and schematics are fixed. They cannot be parameterized. -Ken
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Andrew Beckett

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Re: The problem of bus width of output terminal
Reply #4 - Mar 5^th, 2020, 7:03am

You might find my article on Cadence Online Support helpful: How to create a VerilogA model of a DAC with a variable width bus input

This shows how you can have a Verilog-A model with a variable width bus (for the symbol and the Verilog-A view itself). It is possible, it's just slightly tricky because you have to build a PCell to do the work to make the bus width variable.

Regards,

Andrew.

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