Seems like a "soft limiter is the solution. I notice it still has if statements but is continuous around them so maybe that's okay
Code:https://simplis.com/documentation/simetrix/verilog_a_reference/topics/writingverilog_acode_asoftlimiter.htm
Code:'include "disciplines.vams"
module soft_limiter(in, out) ;
electrical in, out ;
parameter real vlow=-1.0,
vhigh=1.0,
soft=0.1 from (0:1.0) ;
localparam real band = (vhigh-vlow)*soft,
vlow_1 = vlow+band,
vhigh_1 = vhigh-band ;
real vin ;
analog
begin
@(initial_step)
if (vhigh<vlow)
begin
$strobe("Lower limit must be less than higher limit") ;
$finish ;
end
vin = V(in) ;
if (vin>vhigh_1)
V(out) <+ vhigh_1+band*(1.0-exp(-(vin-vhigh_1)/band));
else if (vin<vlow_1)
V(out) <+ vlow_1-band*(1.0-exp((vin-vlow_1)/band)) ;
else
V(out) <+ vin ;
end
endmodule