Dear Ken (& others of course),
Thank you very much, Ken, in writing back. The 1st part of your answer is and was clear to me ( = that the noise output of a T&H (stand-alone = with no circuit connected afterwards) is 0.5 times the one of the S&H at low frequencies), as I perfectly could already gain out of your equations presented your excellent paper “Simulating Switched-Capacitor Filters with SpectreRF”.
However, my 2 core questions are related to the 2nd part of your answer, as soon as the integrator (in open loop) is added - and here, things start becoming unclear to me:
You write, “the integrator is acting as a S&H”. It seems so: This behavior I also saw from the Cadence circuit simulation results, but this is exactly my following point / question:
1) WHY is the integrator acting (itself) as a S&H? It seems, that no paper, nothing describe this in a decent way - they all do some more or less complicated math equations and/or optimizing something, but not explaining properly in simple words / block diagram the concept behind: For me, the circuit stays still a T&H (and therefore duty cycle 0.5), just next to it now an integrator connected. Therefore, as I have written, I WOULD HAVE EXPECTED a Root-Spectral-Density (RSD) simulation result at low frequencies resembling the TRACK & Hold (454 uV / 10000 = 45 nV ). Ok, there is current flowing away in the 2nd phase but the switch is still 50% open and closed, so I thought should be still a T&H !?
In contrast to my expectation, as you clearly write, the integrator ITSELF is somehow already acting as a S&H. Apparently, there is no need to attach additionally your nice “Ideal S&H” after it, as the sim. results show in this case the very same value (903 uV) if one compares the nodes “Vo” and “Vo_ext”. So:
2) What would be a CORRECT MODEL / BLOCK DIAGRAM for this circuit? I mean, WHERE, AT WHICH STAGE, conceptually does this sampling “inside” the integrator happen?? If you please could e.g. draw a clear block diagram, similar to those examples below?? This would definitely help! As written in my detailed previous post, should I do for the model option a), or b), or c), or any other combination??? And how to do this also correctly for the more general case, if then the 2 capacitors are not equal anymore (Sampling cap “Cs” and feedback cap “Cf”)! (There of course will appear an additional gain block with value Cs/Cf in the chain). But place before or after that gain block e.g. the sampling block / ZOH which has non-negligible amplitude drop and phase shift at fs/2? Ok, up to now it is still a linear system model but if I need to instantiate it somewhere, where would be the correct place to put it into the whole chain? When I then want to model e.g. additionally the supply limit of the integrator (which is usually done with a saturation block inside the discrete-time integrator loop), then, the model should still somehow yield correct results (at least from the concept point of view) compared to the circuit reference. So where to place then the “sampling” block correctly (because the integrator is acting as a S&H)??
The value of the sim. results of option a) are not so bad at least for the simple case (Cs=Cf, no model of the supply limit, etc.) when I try in Matlab with your equations, Ken, compared to the Cadence circuit reference (see the fat red and black line in the figure of my previous post). But conceptually I might be doing a wrong thing here, since I place a S&H block BEFORE the integrator, and we saw from simulation, if I just leave away the integrator in the real schematics, it is a T&H, not a S&H, so maybe option c) is the better choice?
AND, AS I SAID, IT’S NO GOOD ENGINEERING TO JUST TRY COMBINATIONS. I WANT AND NEED TO UNDERSTAND: AT WHICH STAGE throughout the whole model chain TO INSTANTIATE WHICH ITEMS AND WHY, BUT THEREFORE I NEED YOUR HELP!
So making concrete things, where to place exactly these S&H / ZOH elements e.g. into the following linear model of a simple switched-cap integrator I established and why exactly here??? The kT/C noise represents the input source “Vi”, but then ???
Many 1000 thanks for a profound answer in advance,