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Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in (Read 119 times)
bernd2700
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Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Nov 12th, 2021, 2:31am
 
I indeed found a much simpler and clearer formulation of my core question, here it is (but therefore without all the Matlab equation proofes, these can be found in my detailled post some days ago).

Root-spectral density @ low frequencies obtained with Cadence PNoise analysis for the following:

Track-and-Hold circuit stand-alone:
T&H stand-alone:               (Node “Vcs”):          ~ 45.4 nV/sqrt(Hz)
Sampled with Ideal S&H:    (Node “Vcs_ext”):    ~ 90.3 nV/sqrt(Hz)

    ((See attached picture 1))

Complete integrator circuit:
Node “Vo” :         903 uVrms/sqrt(Hz)
Node “Vo_ext” :   903 uVrms/sqrt(Hz)     (here exactly the same as the result for node “Vo”)

    ((See attached picture 2))

If we divide this result by the open loop gain of 10000, we get again the 90.3 nVrms/sqrt(Hz). So with just now adding the (lossy, open-loop) integrator to the stand-alone T&H, the whole circuit now suddenly resembles a Sample & Hold (S&H), not anymore a T&H. Why?? The first part is still a T&H circuit! What is a correct theoretical model for this complete stuff?

Thank you very much for any answer, any hint, anything in advance!
Bernd2700

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kTC_Noise_TrackAndHold_Stand-alone_RSD_001.png
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bernd2700
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Re: Summarized phrasing of my core question "kT/C noise combined with an integrator"
Reply #1 - Nov 12th, 2021, 2:32am
 
Complete integrator
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kTC_Noise_Complete_switched-cap_integrator_RSD.png
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Ken Kundert
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Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Reply #2 - Nov 12th, 2021, 12:29pm
 
Quote:
the whole circuit now suddenly resembles a Sample & Hold (S&H), not anymore a T&H. Why??

The difference between your T&H and your S&H is that the duty cycle of the output of the T&H is roughly 50% whereas the duty cycle of the S&H is roughly 100%.  That explains why the noise the output of the T&H is roughly half that of the S&H.

Your integrator is acting as a S&H.  The duty cycle at the output the integrator is roughly 100%.

You do not need pnoise to see this phenomenon. You can also see it with a PAC analysis.

-Ken
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bernd2700
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Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Reply #3 - Nov 15th, 2021, 6:57am
 
Dear Ken (& others of course),

Thank you very much, Ken, in writing back. The 1st part of your answer is and was clear to me ( = that the noise output of a T&H (stand-alone = with no circuit connected afterwards) is 0.5 times the one of the S&H at low frequencies), as I perfectly could already gain out of your equations presented your excellent paper “Simulating Switched-Capacitor Filters with SpectreRF”.

However, my 2 core questions are related to the 2nd part of your answer, as soon as the integrator (in open loop) is added - and here, things start becoming unclear to me:

You write, “the integrator is acting as a S&H”. It seems so: This behavior I also saw from the Cadence circuit simulation results, but this is exactly my following point / question:

1) WHY is the integrator acting (itself) as a S&H? It seems, that no paper, nothing describe this in a decent way - they all do some more or less complicated math equations and/or optimizing something, but not explaining properly in simple words / block diagram the concept behind: For me, the circuit stays still a T&H (and therefore duty cycle 0.5), just next to it now an integrator connected. Therefore, as I have written, I WOULD HAVE EXPECTED a Root-Spectral-Density (RSD) simulation result at low frequencies resembling the TRACK & Hold (454 uV / 10000 = 45 nV ). Ok, there is current flowing away in the 2nd phase but the switch is still 50% open and closed, so I thought should be still a T&H !?

In contrast to my expectation, as you clearly write, the integrator ITSELF is somehow already acting as a S&H. Apparently, there is no need to attach additionally your nice “Ideal S&H” after it, as the sim. results show in this case the very same value (903 uV) if one compares the nodes “Vo” and “Vo_ext”. So:

2) What would be a CORRECT MODEL / BLOCK DIAGRAM for this circuit? I mean, WHERE, AT WHICH STAGE, conceptually does this sampling “inside” the integrator happen?? If you please could e.g. draw a clear block diagram, similar to those examples below?? This would definitely help! As written in my detailed previous post, should I do for the model option a), or b), or c), or any other combination??? And how to do this also correctly for the more general case, if then the 2 capacitors are not equal anymore (Sampling cap “Cs” and feedback cap “Cf”)! (There of course will appear an additional gain block with value Cs/Cf in the chain). But place before or after that gain block e.g. the sampling block / ZOH which has non-negligible amplitude drop and phase shift at fs/2? Ok, up to now it is still a linear system model but if I need to instantiate it somewhere, where would be the correct place to put it into the whole chain? When I then want to model e.g. additionally the supply limit of the integrator (which is usually done with a saturation block inside the discrete-time integrator loop), then, the model should still somehow yield correct results (at least from the concept point of view) compared to the circuit reference. So where to place then the “sampling” block correctly (because the integrator is acting as a S&H)??
The value of the sim. results of option a) are not so bad at least for the simple case (Cs=Cf, no model of the supply limit, etc.) when I try in Matlab with your equations, Ken, compared to the Cadence circuit reference (see the fat red and black line in the figure of my previous post). But conceptually I might be doing a wrong thing here, since I place a S&H block BEFORE the integrator, and we saw from simulation, if I just leave away the integrator in the real schematics, it is a T&H, not a S&H, so maybe option c) is the better choice?
AND, AS I SAID, IT’S NO GOOD ENGINEERING TO JUST TRY COMBINATIONS. I WANT AND NEED TO UNDERSTAND: AT WHICH STAGE throughout the whole model chain TO INSTANTIATE WHICH ITEMS AND WHY, BUT THEREFORE I NEED YOUR HELP!


So making concrete things, where to place exactly these S&H / ZOH elements e.g. into the following linear model of a simple switched-cap integrator I established and why exactly here??? The kT/C noise represents the input source “Vi”, but then ???

Many 1000 thanks for a profound answer in advance,
Bernd2700

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DesignersGuide_Forum_post_SC_kTC_noise_Comparison_sim_Cadence_Theory_with_subsequent_integrator_151121_Fig.png
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Ken Kundert
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Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Reply #4 - Nov 16th, 2021, 10:32pm
 
Too many questions all at once.  I need to focus on one at a time.  So lets focus on #1.

The integrator samples its input when the switch closes. At that time the output voltage changes so that all the charge on Cs flows onto Cf. Once equilibrium has been reached, the output remains unchanged even when the opens again.  This is the behavior of a sample & hold.  The input is sampled when the switch closes and the output is held until the next sample.

This contrasts with the input stage. There, when the switch closes the stage goes into track mode and the output of the state tracks the input.  When the switch opens the stage goes into hold mode.

-Ken
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bernd2700
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Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Reply #5 - Nov 22nd, 2021, 3:55am
 
Dear Ken ( & others),

Thank you for your reply! Ok, let’s proceed to question 2:
I have drawn a detailed timing diagram of the circuit for that.

((see attached timing diagram))

What we see happening in the real circuit: First comes the input tracking phase. Then, as soon as switch 1 ( = switch connected to phase 1) opens = going to low state at time point #1, also the sampling occurs. The voltage on the cap “Cs” ( = Vcs) remains now constant ( = the on-state resistor noise is gone) until time point #2. Here, phase 2 gets high and switch 2 closes, resulting in an instantaneous charge sharing between the 2 capacitors. Then the integration phase follows.

What could happen / happens conceptually? :
So, the timing diagram produces the following sequence: First comes the tracking phase, then the sampling, then, finally, if we leave out the charge sharing phase, the integrating phase (and so the voltage amplification between the 2 caps).
Because you, Ken, confirm, that the whole circuit “is acting as a S&H”, I am thinking that option a) could be fine for a valid model to obtain the output-referred noise?! So, I followed the steps according to option a) by equations (in Matlab):

Step (1.) Building “kT/C noise together with a S&H”: ([Basically from Ken Kundert’s paper])
m_SH = 0;   % Duty-cycle, for the S&H it is 0.
Vn_SH_RSD_vec = sqrt( ((1-m_SH)*sinc(f_vec.*(1-m_SH)*Ts)).^2*2*k*T/(Cs*fs) );           % [Vrms/sqrt(Hz)]


Step (2.) Building the “transfer-function (tf) of a lossy integrator”:
f = 1 - 1 / ( Aol / ( Cs / Cf ) );      % Models lossy (= limited DC-gain) integrator.
Int_z = - Cs / Cf * z.^-0.5 ./ ( 1 - z.^-1 * f);  % This is the exact model (with "z^-0.5") for this type of circuit


Step (3.) = (1.) * (2.) = Multiplying the “(kT/C noise with S&H)” with the “(tf. of the integrator)”:
kTCs_only_SH_times_tf_Integrator_DT = Vn_SH_RSD_vec' .* abs(Int_z');

Step (4.) Plot:
semilogx( f_vec , 20*log10( kTCs_only_SH_times_tf_Integrator_DT ) , 'r' , 'LineWidth' , 3 );

==> Is my thinking = the resulting block diagram option a) correct for this circuit? Please “confirm” or “disagree”!
==> Why then the Cadence PNoise result show nulls (= sudden drop downs) at fs = 1 kHz, 10*fs, 100*fs? (See thick black line, recalling the picture from my previous, detailed, post.) However, in the theoretical (Matlab) tick red line these are missing. Why? So: Am I doing here conceptually something wrong with taking “option a)” as a model for this circuit or are these nulls just an artefact of the Cadence PNoise analysis?

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SC-Integrator_SE_ParSen_Dly_RisingP1_NoDblSmp_Noise_TimingDiagramOnly__low_res.jpg
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bernd2700
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Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Reply #6 - Nov 22nd, 2021, 4:00am
 
Recalling the picture again from my previous (detailed) post: ((Picture: "Fig8 kTC noise only with subsequent integrator.jpg"))
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Ken Kundert
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Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Reply #7 - Nov 24th, 2021, 11:35pm
 
I am not going to check your equations and your models. That would take too much time.

The block diagram looks right.

The nulls in the transfer function at 1 kHz, 10*fs, 100*fs is a plotting artifact.  There are actually sin(x)/x nulls at multiples of the clock frequency, but you are not using enough points in the plot to see all the nulls.
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