Complete integrator

Dear Ken (& others of course),

Thank you very much, Ken, in writing back. The 1st part of your answer is and was clear to me ( = that the noise output of a T&H (stand-alone = with no circuit connected afterwards) is 0.5 times the one of the S&H at low frequencies), as I perfectly could already gain out of your equations presented your excellent paper “Simulating Switched-Capacitor Filters with SpectreRF”.

However, my 2 core questions are related to the 2nd part of your answer, as soon as the integrator (in open loop) is added - and here, things start becoming unclear to me:

You write, “the integrator is acting as a S&H”. It seems so: This behavior I also saw from the Cadence circuit simulation results, but this is exactly my following point / question:

1) WHY is the integrator acting (itself) as a S&H? It seems, that no paper, nothing describe this in a decent way - they all do some more or less complicated math equations and/or optimizing something, but not explaining properly in simple words / block diagram the concept behind: For me, the circuit stays still a T&H (and therefore duty cycle 0.5), just next to it now an integrator connected. Therefore, as I have written, I WOULD HAVE EXPECTED a Root-Spectral-Density (RSD) simulation result at low frequencies resembling the TRACK & Hold (454 uV / 10000 = 45 nV ). Ok, there is current flowing away in the 2nd phase but the switch is still 50% open and closed, so I thought should be still a T&H !?

In contrast to my expectation, as you clearly write, the integrator ITSELF is somehow already acting as a S&H. Apparently, there is no need to attach additionally your nice “Ideal S&H” after it, as the sim. results show in this case the very same value (903 uV) if one compares the nodes “Vo” and “Vo_ext”. So:

2) What would be a CORRECT MODEL / BLOCK DIAGRAM for this circuit? I mean, WHERE, AT WHICH STAGE, conceptually does this sampling “inside” the integrator happen?? If you please could e.g. draw a clear block diagram, similar to those examples below?? This would definitely help! As written in my detailed previous post, should I do for the model option a), or b), or c), or any other combination??? And how to do this also correctly for the more general case, if then the 2 capacitors are not equal anymore (Sampling cap “Cs” and feedback cap “Cf”)! (There of course will appear an additional gain block with value Cs/Cf in the chain). But place before or after that gain block e.g. the sampling block / ZOH which has non-negligible amplitude drop and phase shift at fs/2? Ok, up to now it is still a linear system model but if I need to instantiate it somewhere, where would be the correct place to put it into the whole chain? When I then want to model e.g. additionally the supply limit of the integrator (which is usually done with a saturation block inside the discrete-time integrator loop), then, the model should still somehow yield correct results (at least from the concept point of view) compared to the circuit reference. So where to place then the “sampling” block correctly (because the integrator is acting as a S&H)??
The value of the sim. results of option a) are not so bad at least for the simple case (Cs=Cf, no model of the supply limit, etc.) when I try in Matlab with your equations, Ken, compared to the Cadence circuit reference (see the fat red and black line in the figure of my previous post). But conceptually I might be doing a wrong thing here, since I place a S&H block BEFORE the integrator, and we saw from simulation, if I just leave away the integrator in the real schematics, it is a T&H, not a S&H, so maybe option c) is the better choice?
AND, AS I SAID, IT’S NO GOOD ENGINEERING TO JUST TRY COMBINATIONS. I WANT AND NEED TO UNDERSTAND: AT WHICH STAGE throughout the whole model chain TO INSTANTIATE WHICH ITEMS AND WHY, BUT THEREFORE I NEED YOUR HELP!


So making concrete things, where to place exactly these S&H / ZOH elements e.g. into the following linear model of a simple switched-cap integrator I established and why exactly here??? The kT/C noise represents the input source “Vi”, but then ???

Many 1000 thanks for a profound answer in advance,
Bernd2700

Dear Ken ( & others),

Thank you for your reply! Ok, let’s proceed to question 2:
I have drawn a detailed timing diagram of the circuit for that.

((see attached timing diagram))

What we see happening in the real circuit: First comes the input tracking phase. Then, as soon as switch 1 ( = switch connected to phase 1) opens = going to low state at time point #1, also the sampling occurs. The voltage on the cap “Cs” ( = Vcs) remains now constant ( = the on-state resistor noise is gone) until time point #2. Here, phase 2 gets high and switch 2 closes, resulting in an instantaneous charge sharing between the 2 capacitors. Then the integration phase follows.

What could happen / happens conceptually? :
So, the timing diagram produces the following sequence: First comes the tracking phase, then the sampling, then, finally, if we leave out the charge sharing phase, the integrating phase (and so the voltage amplification between the 2 caps).
Because you, Ken, confirm, that the whole circuit “is acting as a S&H”, I am thinking that option a) could be fine for a valid model to obtain the output-referred noise?! So, I followed the steps according to option a) by equations (in Matlab):

Step (1.) Building “kT/C noise together with a S&H”: ([Basically from Ken Kundert’s paper])
m_SH = 0;   % Duty-cycle, for the S&H it is 0.
Vn_SH_RSD_vec = sqrt( ((1-m_SH)*sinc(f_vec.*(1-m_SH)*Ts)).^2*2*k*T/(Cs*fs) );           % [Vrms/sqrt(Hz)]

Step (2.) Building the “transfer-function (tf) of a lossy integrator”:
f = 1 - 1 / ( Aol / ( Cs / Cf ) );      % Models lossy (= limited DC-gain) integrator.
Int_z = - Cs / Cf * z.^-0.5 ./ ( 1 - z.^-1 * f);  % This is the exact model (with "z^-0.5") for this type of circuit

Step (3.) = (1.) * (2.) = Multiplying the “(kT/C noise with S&H)” with the “(tf. of the integrator)”:
kTCs_only_SH_times_tf_Integrator_DT = Vn_SH_RSD_vec' .* abs(Int_z');

Step (4.) Plot:
semilogx( f_vec , 20*log10( kTCs_only_SH_times_tf_Integrator_DT ) , 'r' , 'LineWidth' , 3 );

==> Is my thinking = the resulting block diagram option a) correct for this circuit? Please “confirm” or “disagree”!
==> Why then the Cadence PNoise result show nulls (= sudden drop downs) at fs = 1 kHz, 10*fs, 100*fs? (See thick black line, recalling the picture from my previous, detailed, post.) However, in the theoretical (Matlab) tick red line these are missing. Why? So: Am I doing here conceptually something wrong with taking “option a)” as a model for this circuit or are these nulls just an artefact of the Cadence PNoise analysis?

I am not going to check your equations and your models. That would take too much time.

The block diagram looks right.

The nulls in the transfer function at 1 kHz, 10*fs, 100*fs is a plotting artifact.  There are actually sin(x)/x nulls at multiples of the clock frequency, but you are not using enough points in the plot to see all the nulls.

Cadence_Cs_Cf_1F_PAC_results_Nodes_Vo_Vo_ext.png

I'm afraid I have no experience with sampled PAC and cannot offer much. Nulls that go to infinity (poles) suggest that there is some normalization occurring, and the normalization is going to zero at those frequencies.  You should look more closely to see if they are really going to infinity, or to the dc gain of the amplifier.  Its not clear from the graph.

As for the nulls being a display artifact, I have experienced them many times and they have always turned out to be so.  And when using a logarithmic sweep it is common to only see the nulls every factor of 10.  I recommend that you request many more points and then zoom in.  You can also try switching to a linear sweep and make sure there are points at all the harmonics of the clock.

-Ken

Dear Ken (& others),

However, one question remains to this whole topic.

In short:
The real Cadence switched-cap. (SC.) integrator circuit (from the previous posts ; in below graph in green color) modelled by ...
a) ... a pure Discrete-Time (DT) integrator Matlab model (in “z”) is fine and I understand all effects (red).
b) ... a Continuous-Time (CT) integrator Matlab model (in “s”) which is then sampled by a ZOH (S&H) to get the DT response:
  ==>   Why the hell it seems I have to DIVIDE by the ZOH (S&H) transfer-function and NOT to MULTIPLY by it to get matching results (blue) to the Cadence SC circuit (green)??  (Bode diagram magnitude at least)

In more detail:
That others can follow, I now describe this question a bit in-depth:

A Zero-Order-Hold (ZOH) (Sample & Hold S&H) block stand-alone:
First, we watch the Bode plot for this block stand-alone: The “nulls” go DOWN to –INFINITY (Here, because of “only” 1meg. points/dec., the first ones just go down to ca. -125 dB.). We see, at fs/2 its Bode plot has a gain of ca. -4 dB and a phase shift of -90° compared to the DC value of 0 dB / 0°.
(Source: "https://electronics.stackexchange.com/questions/206482/exactly-what-is-the-role
-of-the-zero-order-hold-in-a-hybrid-analog-digital-sampl": "Many textbooks leave out the T factor in the denominator of the transfer function and that is a mistake.": (1-exp(-s*Ts))/(s*Ts);)

My real Cadence SC. integrator circuit (= my reference ; green):
In the attached figure, the real Cadence sw.-cap. circuit (in green color) shows that the “nulls” at 1, 2, 3 ... * fs go UP, but only to +80 dB = to the DC-gain of the integrator, as it can be read in the previous posts. To obtain this Bode plot, as said, I do the “PAC sampled” analysis. This SC. circuit is my reference, and this I want to model with the following models:

Pure DT integrator model (in “z”) (red):
In a DT (discrete-time) model in “z” - domain, the “nulls” also go UP and also to this +80 dB level because theory says so (symmetry around fs/2 as presented in my previous post). In this pure DT model, the integrator has unlimited speed, therefore there is no kink visible at ~ 100 kHz.

CT integrator model (in “s”) DIVIDED by the ZOH (S&H) block (blue):
Here, I would like to model my real Cadence SC. circuit with a Continuous-Time (CT) integrator (in “s” - domain) Matlab model. To account equivalently for the “_SAMPLED” option of the Cadence PAC analysis in the real circuit also in this model, for me, this means (maybe I am wrong here??) I logically would have to subsequently MULTIPLY the integrator output by the S&H transfer function. This is my interpretation, because the strange thing is (= above question), obviously, I have to DIVIDE the integrator output by the ZOH transfer function, and not to multiply by it in order that the “nulls” go also up, and not down, as in the S&H stand-alone case. Then the Bode diagram of this result (blue color) matches approx. the real Cadence SC. circuit (green), apart from the nulls going up higher than just to the +80 dB DC gain limit. Of course, then, there is no symmetry around fs/2 anymore, since the open-loop DC gain is just +80 dB and in this model, the nulls go up, but to +infinity, not to just +80 dB (ok, I also do not have a DT signal which is valid only at 1/fs time points but still a CT signal whose value is held constant until the next point in time). However,
==> What is wrong with this procedure for a CT model / how to do correctly?

Thanks for any hint in advance,
bernd2700