Designer’s Guide Community

Pages: 1 2 3 ... 14

Subject	Started by	Replies	Views	Last post
Calibre, LVS, new layer	balshoy	2	3171	Jan 26^th, 2024, 8:36am By: ajithkv
POLY1 must be covered by N+ or P+ implant layer @Umc40lp using Calibre	Ramakrishna RSSM	1	1196	Jan 26^th, 2024, 8:16am By: ajithkv
GCD fill layer in 28nm technology	vlsi_design	1	589	Jan 26^th, 2024, 8:10am By: ajithkv
Black boxing in calibre for IO cells	vlsi_design	1	815	Jan 26^th, 2024, 8:06am By: ajithkv
Cap extraction of an IC PAD	vlsi_design	1	756	Jun 21^st, 2022, 7:12am By: Maks
PEX R+C Extraction: How to set minimum cap and minimum R	S.ARYA	1	1322	Feb 12^th, 2021, 8:38pm By: Maks
Circuit simulation and parasitics: do we need more speed, or more insight (or bo	Maks	0	779	Nov 7^th, 2020, 3:14pm By: Maks
PEX Extraction Issues	vm511	2	1518	Mar 4^th, 2020, 9:18pm By: vm511
Short circuit with VDD3ALLP pad on C35B4C3 AMS technology	eddy19	1	1228	Sep 13^th, 2019, 8:00am By: eddy19
Extract parameters for custom Verilog-A models	georgtree	2	3054	Jan 29^th, 2019, 6:25pm By: Ziauddin
Importing Files from ASITIC (CIF files) Into Cadence	repah	1	2289	Aug 6^th, 2018, 2:12pm By: Andrew Beckett
Post layout simulations	raja.cedt	13	14357	Nov 5^th, 2017, 10:38am By: Maks
Post Layout Simulation For Mixed signal Verification Environment	Gp	3	1962	Jul 19^th, 2017, 8:06am By: Maks
Deep nwell devices in tsmc65nm	mixed_signal	1	3298	Apr 14^th, 2017, 5:06pm By: Maks
Simulating a high Q MKID in Sonnet	lefebre	1	2784	Apr 14^th, 2017, 4:59pm By: Maks
Substrate parameters values?!!!	Hamid1982	1	1229	Apr 14^th, 2017, 4:56pm By: Maks
PVS QRC / Calibre PEX both extracting 3x lower Resistance	polly	1	3808	Apr 14^th, 2017, 4:42pm By: Maks
cmos active inductor......	ofaruqe20	1	2298	Mar 25^th, 2017, 2:31am By: Andrew Beckett
Managing PVS-LVS from a GUI	Lala878	0	1994	Dec 7^th, 2016, 12:13am By: Lala878
X Y snap spacing for layout window	mixed_signal	3	4915	Dec 6^th, 2016, 11:47pm By: Lala878

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