Designer’s Guide Community

Pages: 1 2 3 ... 14

Subject	Started by	Replies	Views	Last post
Cap extraction of an IC PAD	vlsi_design	1	35	Jun 21^st, 2022, 7:12am By: Maks
PEX R+C Extraction: How to set minimum cap and minimum R	S.ARYA	1	591	Feb 12^th, 2021, 8:38pm By: Maks
Circuit simulation and parasitics: do we need more speed, or more insight (or bo	Maks	0	308	Nov 7^th, 2020, 3:14pm By: Maks
PEX Extraction Issues	vm511	2	655	Mar 4^th, 2020, 9:18pm By: vm511
Short circuit with VDD3ALLP pad on C35B4C3 AMS technology	eddy19	1	528	Sep 13^th, 2019, 8:00am By: eddy19
Extract parameters for custom Verilog-A models	georgtree	2	2145	Jan 29^th, 2019, 6:25pm By: Ziauddin
Importing Files from ASITIC (CIF files) Into Cadence	repah	1	1478	Aug 6^th, 2018, 2:12pm By: Andrew Beckett
Post layout simulations	raja.cedt	13	11134	Nov 5^th, 2017, 10:38am By: Maks
Post Layout Simulation For Mixed signal Verification Environment	Gp	3	767	Jul 19^th, 2017, 8:06am By: Maks
Calibre, LVS, new layer	balshoy	1	1971	Jun 23^rd, 2017, 12:06am By: Maks
POLY1 must be covered by N+ or P+ implant layer @Umc40lp using Calibre	Ramakrishna RSSM	0	537	May 7^th, 2017, 2:44am By: Ramakrishna RSSM
Deep nwell devices in tsmc65nm	mixed_signal	1	2590	Apr 14^th, 2017, 5:06pm By: Maks
Simulating a high Q MKID in Sonnet	lefebre	1	2002	Apr 14^th, 2017, 4:59pm By: Maks
Substrate parameters values?!!!	Hamid1982	1	542	Apr 14^th, 2017, 4:56pm By: Maks
PVS QRC / Calibre PEX both extracting 3x lower Resistance	polly	1	3058	Apr 14^th, 2017, 4:42pm By: Maks
cmos active inductor......	ofaruqe20	1	1548	Mar 25^th, 2017, 2:31am By: Andrew Beckett
Managing PVS-LVS from a GUI	Jelena	0	1468	Dec 7^th, 2016, 12:13am By: Jelena
X Y snap spacing for layout window	mixed_signal	3	3781	Dec 6^th, 2016, 11:47pm By: Jelena
plotting node waveform from layout	VNF	1	2804	Jul 5^th, 2016, 3:08am By: pazhasi
Incorrect hierarchical Calibre PEXR extraction	pazhasi	0	1688	Jul 5^th, 2016, 2:35am By: pazhasi

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