Designer’s Guide Community

Pages: 1 2 3 ... 14

Subject	Started by	Replies	Views	Last post
Black boxing in calibre for IO cells	vlsi_design	0	55	Jul 30^th, 2022, 9:49am By: vlsi_design
GCD fill layer in 28nm technology	vlsi_design	0	37	Jul 24^th, 2022, 6:55pm By: vlsi_design
Cap extraction of an IC PAD	vlsi_design	1	99	Jun 21^st, 2022, 7:12am By: Maks
PEX R+C Extraction: How to set minimum cap and minimum R	S.ARYA	1	637	Feb 12^th, 2021, 8:38pm By: Maks
Circuit simulation and parasitics: do we need more speed, or more insight (or bo	Maks	0	336	Nov 7^th, 2020, 3:14pm By: Maks
PEX Extraction Issues	vm511	2	701	Mar 4^th, 2020, 9:18pm By: vm511
Short circuit with VDD3ALLP pad on C35B4C3 AMS technology	eddy19	1	563	Sep 13^th, 2019, 8:00am By: eddy19
Extract parameters for custom Verilog-A models	georgtree	2	2202	Jan 29^th, 2019, 6:25pm By: Ziauddin
Importing Files from ASITIC (CIF files) Into Cadence	repah	1	1537	Aug 6^th, 2018, 2:12pm By: Andrew Beckett
Post layout simulations	raja.cedt	13	11405	Nov 5^th, 2017, 10:38am By: Maks
Post Layout Simulation For Mixed signal Verification Environment	Gp	3	838	Jul 19^th, 2017, 8:06am By: Maks
Calibre, LVS, new layer	balshoy	1	2017	Jun 23^rd, 2017, 12:06am By: Maks
POLY1 must be covered by N+ or P+ implant layer @Umc40lp using Calibre	Ramakrishna RSSM	0	570	May 7^th, 2017, 2:44am By: Ramakrishna RSSM
Deep nwell devices in tsmc65nm	mixed_signal	1	2631	Apr 14^th, 2017, 5:06pm By: Maks
Simulating a high Q MKID in Sonnet	lefebre	1	2056	Apr 14^th, 2017, 4:59pm By: Maks
Substrate parameters values?!!!	Hamid1982	1	582	Apr 14^th, 2017, 4:56pm By: Maks
PVS QRC / Calibre PEX both extracting 3x lower Resistance	polly	1	3110	Apr 14^th, 2017, 4:42pm By: Maks
cmos active inductor......	ofaruqe20	1	1633	Mar 25^th, 2017, 2:31am By: Andrew Beckett
Managing PVS-LVS from a GUI	Jelena	0	1493	Dec 7^th, 2016, 12:13am By: Jelena
X Y snap spacing for layout window	mixed_signal	3	3847	Dec 6^th, 2016, 11:47pm By: Jelena

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