My recent article on this topic on LinkedIn generated a lot of feedback, from the community of IC designers and layout engineers.
I am placing a pointer to that article and discussion, in a hope that it may be useful for some people here, who struggle with parasitics in advanced nodes and in high-speed or precision analog designs.
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IC layout parasitics are playing increasingly important role in IC designs.

How to properly handle the parasitics?
Is speed of simulation (SPICE, IR/EM, timing, etc.) the only problem, or are there other important aspects beyond simulation speed - like deeper insight, better visualization, better identification and ranking of the critical parasitic elements and layout layers or shapes?

I discuss these and related questions in my LinkedIn article "Circuit simulation and parasitics: do we need more speed, or more insight (or both)?"

Please feel free to share your thoughts and experiences on this topic.

https://www.linkedin.com/pulse/circuit-simulation-parasitics-do-we-need-more-spe...