I'll have to disagree with deba about the "The point of running mixed signal is to ensure only functional verification.".
Post layout simulation is to ensure functionality, and to see how much performance is affected. One example of post layout sim is to see how much slower a SAR ADC has become due to capacitive parasitics. In a mature technology, if we're not hitting the speed spec in post layout C sims, we're not going to hit it in measurements. So we will adjust the layout, or schematic if necessary. Extract, and sim again.
Another example might be capacitive coupling onto a sensitive analog line. Functionally the circuit might work, but maybe the signal-to-distortion ratio dropped by 6 dB and you don't know why. It's important to check specifications.
Anyways, the flow goes something like:
1) Schematic sim results
2) C-extracted sim results, compare with schematic, adjust any major parasitic issues
3) RCC sim, compare with schematic, adjust any major parasitic issues
Now people have varying opinions on the accuracy of RCC sims, whether or not the extraction tool worked correctly or not. The C sim is usually all right, the RCC can sometimes be misleading.
Depending on the size of your extraction, you might also consider parasitic reduction to reduce file size (usually only for RCC).