Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
PIN order in extracted netlist from Calibre PEX	SATurn	0	1766	Dec 9^th, 2015, 1:06pm By: SATurn
High Voltage NMOS in AMS h35 process	preethip	0	1618	Sep 24^th, 2015, 12:53pm By: preethip
tool for RF PCB simulation	Pavel	1	2408	Aug 17^th, 2015, 4:45am By: Frank Wiedmann
HFSS Simulation - Return path	Jim cage	0	1869	Jun 15^th, 2015, 11:20pm By: Jim cage
Error while generating LEF file in Abstract in cadence	VINAY RAO	1	2206	May 7^th, 2015, 2:28am By: boe
calibre pex problem	wang072711	1	2943	Mar 13^th, 2015, 9:49am By: wang072711
Calibre error: virserver.tcl error and RVE server socket has not been initialize	final	0	351	Jan 27^th, 2015, 8:36pm By: final
Spectre_simulator : Post layout verification problem	ghegde	6	8915	Dec 11^th, 2014, 7:14am By: ghegde
QRC simulation problem	adelaid	3	3191	Sep 25^th, 2014, 2:11am By: boe
EM Simulation	AZADBAKHT	3	3188	Sep 17^th, 2014, 6:33am By: irisaru
Help: contact via missing when width is increased for poly-silicon resistor.	Jacki	2	2550	Jul 10^th, 2014, 9:21am By: boe
How to do double guard ring without problem of diodenwx?	Jacki	0	1927	Jul 5^th, 2014, 7:59am By: Jacki
Bad device in LVS check.	Jacki	5	6499	Jun 22^nd, 2014, 4:03pm By: Jacki
How to define Via/contact when transfer layout from old designkits to new one?	Jacki	1	2051	Jun 17^th, 2014, 3:58pm By: Jacki
Creating Calibreview in Virtuosuo (IC5141)	samiran	1	265	Jun 2^nd, 2014, 11:20am By: Jacki
Writing to .csv while doing corner in ADEXL using OCEAN.	VINAY RAO	0	1780	May 5^th, 2014, 9:11pm By: VINAY RAO
Calibre with PSPICE netlist	x.q.w.	0	1749	Apr 15^th, 2014, 2:33pm By: x.q.w.
bondwire simulated with hfss	baohulu	0	2925	Apr 11^th, 2014, 11:59pm By: baohulu
Cannot enable LVS push device.	Jacki	1	4516	Apr 2^nd, 2014, 1:50pm By: Jacki
HIT KIT Utilities FILLPATTERN	pinkfloyd	2	2565	Mar 17^th, 2014, 9:57am By: Jacki

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