Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Parasitic extraction of a metal square in cmos process	mixed_signal	1	2141	Mar 21^st, 2016, 4:49pm By: raja.cedt
Calibre pex extraction: avoid RF model extraction	mixed_signal	0	2130	Feb 11^th, 2016, 9:56pm By: mixed_signal
PIN order in extracted netlist from Calibre PEX	SATurn	0	1945	Dec 9^th, 2015, 1:06pm By: SATurn
High Voltage NMOS in AMS h35 process	preethip	0	1777	Sep 24^th, 2015, 12:53pm By: preethip
tool for RF PCB simulation	Pavel	1	2652	Aug 17^th, 2015, 4:45am By: Frank Wiedmann
HFSS Simulation - Return path	Jim cage	0	2033	Jun 15^th, 2015, 11:20pm By: Jim cage
Error while generating LEF file in Abstract in cadence	VINAY RAO	1	2434	May 7^th, 2015, 2:28am By: boe
calibre pex problem	wang072711	1	3191	Mar 13^th, 2015, 9:49am By: wang072711
Calibre error: virserver.tcl error and RVE server socket has not been initialize	final	0	719	Jan 27^th, 2015, 8:36pm By: final
Spectre_simulator : Post layout verification problem	ghegde	6	9810	Dec 11^th, 2014, 7:14am By: ghegde
QRC simulation problem	adelaid	3	3588	Sep 25^th, 2014, 2:11am By: boe
EM Simulation	AZADBAKHT	3	3581	Sep 17^th, 2014, 6:33am By: irisaru
Help: contact via missing when width is increased for poly-silicon resistor.	Jacki	2	2844	Jul 10^th, 2014, 9:21am By: boe
How to do double guard ring without problem of diodenwx?	Jacki	0	2127	Jul 5^th, 2014, 7:59am By: Jacki
Bad device in LVS check.	Jacki	5	7045	Jun 22^nd, 2014, 4:03pm By: Jacki
How to define Via/contact when transfer layout from old designkits to new one?	Jacki	1	2248	Jun 17^th, 2014, 3:58pm By: Jacki
Creating Calibreview in Virtuosuo (IC5141)	samiran	1	595	Jun 2^nd, 2014, 11:20am By: Jacki
Writing to .csv while doing corner in ADEXL using OCEAN.	VINAY RAO	0	1953	May 5^th, 2014, 9:11pm By: VINAY RAO
Calibre with PSPICE netlist	Buyilehu	0	1943	Apr 15^th, 2014, 2:33pm By: Buyilehu
bondwire simulated with hfss	baohulu	0	3088	Apr 11^th, 2014, 11:59pm By: baohulu

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