Hello everyone!
I faced with folowing problem: how can I extract parameters for my Verilog-A model ?
All common models like BSIM, EKV, HiSIM and etc have default implementaions in programs like IC-CAP, MBP, UTMOS. But how can I use such tools for my handwritten models? Does anyone have such experience?
Thank you for help!

You can put the verilog-A coded model into the defined directory of the ICCAP to read the verilog-A model. After that it just as before.

For ICCAP the syntex in the circuit directory is:

ahdl_include "/home/user/hpeesof/veriloga/models_name.va"

Sorry, join the forum late.