The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 29th, 2024, 1:50am
Pages: 1
Send Topic Print
Extract parameters for custom Verilog-A models (Read 2587 times)
georgtree
New Member
*
Offline



Posts: 2

Extract parameters for custom Verilog-A models
Nov 04th, 2017, 12:47pm
 
Hello everyone!
I faced with folowing problem: how can I extract parameters for my Verilog-A model ?
All common models like BSIM, EKV, HiSIM and etc have default implementaions in programs like IC-CAP, MBP, UTMOS. But how can I use such tools for my handwritten models? Does anyone have such experience?
Thank you for help!
Back to top
 
 
View Profile   IP Logged
georgtree
New Member
*
Offline



Posts: 2

Re: Extract parameters for custom Verilog-A models
Reply #1 - Dec 10th, 2017, 4:05am
 
Does anybody know?(
Back to top
 
 
View Profile   IP Logged
Ziauddin
New Member
*
Offline



Posts: 2

Re: Extract parameters for custom Verilog-A models
Reply #2 - Jan 29th, 2019, 6:25pm
 
You can put the verilog-A coded model into the defined directory of the ICCAP to read the verilog-A model. After that it just as before.

For ICCAP the syntex in the circuit directory is:

ahdl_include "/home/user/hpeesof/veriloga/models_name.va"

Sorry, join the forum late.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.