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Mar 29th, 2020, 12:29pm
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PEX Extraction Issues (Read 54 times)
vm511
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PEX Extraction Issues
Mar 04th, 2020, 3:10pm
 
Hi,
I am using Calibre for my layout and post-layout extraction. While my LVS and DRC come to be clean, and even PEX extraction happens without any errors(There's a warning that ideal xcell use gate-level extraction).
However in the calibre view, I can see transistors that I've not instantiated- they are basically to the power rails(near the guard rings). They don't create a problem in this block.
However, now I instantiate this block in another layout(this layout also has BJTs), and while PEX doesn't show any errors or warnings, on saving the calibre view it shows 69 errors - which are mostly because the transistors are shorted (drain of first to source of next and so on), and basically a single net has 2 names because of that (the drain of first mosfet and source of the next). I can just manually delete the labels, but I'm not sure if I've made some errors in my layout, which are somehow not showing up on PEX and LVS, and shows up as these 'extra transistors'?
Can someone please help?

PS. I just realised there was another section for extraction issues - but cant figure out how to move the post. Apologies for the error!
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Maks
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Re: PEX Extraction Issues
Reply #1 - Mar 4th, 2020, 8:27pm
 
If you are doing this in advanced technology (e.g. 16nm or lower nodes), then the LVS may recognize layout devices - i.e. devices that are not present in the schematic, but recognized in layout (they need to be added to a post-layout netlist because they add parasitic device-related capacitance, and have to be accounted for in simulation).

It looks like you are mixing two different entities - net and node.
In post-layout netlist, a net is a connection of metal lines and vias, forming one electrically connected system (node in schematic), and node is instance pin, or port, or a subnode.

Two devices connected by their terminals to one node is unusual, but should not give any errors in simulation.
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vm511
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Re: PEX Extraction Issues
Reply #2 - Mar 4th, 2020, 9:18pm
 
Apologies for the error! I meant the transistors are connected by their nodes due to which label shorting error is being shown when I save the Calibre view. (Since two labels, source and drain are attached to the same node). I'm using a 65 nm process. And these transistors that I'm seeing are near the guard rings. I haven't used BJTs before but I connected the grounded guard rings with the ground terminals of the bjt (base and collector) (in order to make the grounds common). Could this possibly be the issue?


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