Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Help with 3 Key Questions on Analog Circuit Design & Verification	Vodka_JON7	3	1374	Oct 28^th, 2025, 9:34pm By: Ken Kundert
Timer function can't take period input as a parameter	Lala878	1	5144	Jun 11^th, 2024, 4:34am By: Lala878
How to parametrize input bits of a DAC in Verilog A code	Andrea8888	1	2092	Oct 6^th, 2023, 9:22am By: Ken Kundert
VerilogA random DC value	Horror Vacui	3	2685	Sep 11^th, 2023, 7:02pm By: Ken Kundert
How to create a verilog-A testbench to run a sweep of all input pins	avlsi	7	4236	Aug 21^st, 2023, 10:43pm By: Ken Kundert
ADE L Stuck due to timescale definition	Zaidi	2	2535	Mar 27^th, 2023, 4:04am By: Zaidi
How to generate pulse with different amplitude within same transient analysis.	Shah	5	3615	Aug 31^st, 2022, 10:57am By: Ken Kundert
Proper modelling of a current source in verilogAMS.	edstrom	3	4853	Jun 28^th, 2021, 12:20am By: Horror Vacui
Query on a verilogA based pulse generation using a timer blocks.	subtr	4	3687	Jun 14^th, 2021, 10:32pm By: subtr
What is the PSD of noise generated using rdist_normal function?	subtr	11	5924	Aug 13^th, 2019, 10:38am By: subtr
Binary bus evaluation in CASE statement for VerilogA	Guile	3	3679	Jul 11^th, 2019, 6:18am By: Ken Kundert
Help with a verilog-A code	anaspire	1	4506	Jul 31^st, 2018, 10:23am By: Ken Kundert
Fast transient for analog mixed signal verification	deba	2	4404	Jul 28^th, 2018, 1:18am By: deba
Moved: VCO Simulink simulation - Started by: yngwie87 This Topic has been moved to System Simulators by Ken Kundert
Issue with Cadence analog value fetch functions	sgh2050	1	2133	Dec 21^st, 2017, 7:43am By: Andrew Beckett
Assertions inside Connect Modules	sgh2050	1	2032	Nov 30^th, 2017, 1:12am By: nischaybm
PNOISE with a VerilogA oscillator	Horror Vacui	3	6222	Sep 11^th, 2017, 4:07pm By: cheap_salary
creating compile time define switch in .scs file	AMS_ei	5	7958	Jun 2^nd, 2017, 11:37pm By: Andrew Beckett
Test schematic using verilogams testbench	edstrom	1	4388	May 19^th, 2017, 11:02pm By: AMS_ei
use of $dumpvar	Designe_IT	1	2112	May 1^st, 2017, 8:52am By: AMS_ei

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