Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
What is the PSD of noise generated using rdist_normal function?	subtr	11	1013	Aug 13^th, 2019, 11:38am By: subtr
Binary bus evaluation in CASE statement for VerilogA	Guile	3	146	Jul 11^th, 2019, 7:18am By: Ken Kundert
Help with a verilog-A code	anaspire	1	1096	Jul 31^st, 2018, 11:23am By: Ken Kundert
Fast transient for analog mixed signal verification	deba	2	755	Jul 28^th, 2018, 2:18am By: deba
Moved: VCO Simulink simulation - Started by: yngwie87 This Topic has been moved to System Simulators by Ken Kundert
Issue with Cadence analog value fetch functions	sgh2050	1	3	Dec 21^st, 2017, 7:43am By: Andrew Beckett
Assertions inside Connect Modules	sgh2050	1	981	Nov 30^th, 2017, 1:12am By: nischaybm
PNOISE with a VerilogA oscillator	Horror Vacui	3	1995	Sep 11^th, 2017, 5:07pm By: cheap_salary
creating compile time define switch in .scs file	AMS_ei	5	2857	Jun 3^rd, 2017, 12:37am By: Andrew Beckett
Test schematic using verilogams testbench	edstrom	1	1329	May 20^th, 2017, 12:02am By: AMS_ei
use of $dumpvar	Designe_IT	1	3556	May 1^st, 2017, 9:52am By: AMS_ei
Syntax for vsource ramp generator	Rosh	1	0	Apr 25^th, 2017, 11:01am By: AMS_ei
Schematic Model Generator (SMG) tool	Jelena	3	2268	Mar 8^th, 2017, 9:54pm By: Andrew Beckett
Regarding SMG tool	AMS_ei	1	1508	Mar 6^th, 2017, 4:05am By: Andrew Beckett
Verilog AMS co simulation with SV	ranjang	2	3823	Jan 20^th, 2017, 9:21am By: Andrew Beckett
why bode plot of a linear pll model got from spectre is different from simulink?	lwzunique	2	2296	Jan 19^th, 2017, 11:23pm By: lwzunique
Ultrasim syntax for probing current at particular nodes	ranjang	1	3291	Jan 18^th, 2017, 8:17am By: AMS_ei
Verification of AMS based Models	subtr	8	6013	Jan 5^th, 2017, 3:10pm By: subtr
Moved: AMS simulation error - Started by: AMS_ei This Topic has been moved to Timing Simulators by Ken Kundert
If statement VerilogA	verilogGuy	1	2463	Jul 11^th, 2016, 2:33pm By: verilogGuy

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