Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Verification of AMS based Models	subtr	8	7938	Jan 5^th, 2017, 3:10pm By: subtr
Moved: AMS simulation error - Started by: AMS_ei This Topic has been moved to Timing Simulators by Ken Kundert
If statement VerilogA	verilogGuy	1	3066	Jul 11^th, 2016, 2:33pm By: verilogGuy
Question about verilog-A delay function	asifqaiyum	6	7643	Feb 19^th, 2016, 4:01am By: asifqaiyum
Veriloga Auto Parser not working when code saved!	gte558w	0	1604	Jan 8^th, 2016, 9:44am By: gte558w
How to write script in VCS-MX?	Gp	0	1810	Jan 8^th, 2016, 3:01am By: Gp
VAMS clock period monitor- Help!	Rosh	4	4372	Jul 15^th, 2015, 2:15am By: Rosh
Ideal voltage source in spectre	rampat	3	9003	May 13^th, 2015, 8:31am By: Geoffrey_Coram
avoiding singular matrix and zero diagonal messages	suam	1	3435	Nov 9^th, 2014, 3:45pm By: Ken Kundert
Linear Regulator test bench	amruta	7	1256	Nov 6^th, 2014, 10:51am By: amruta
Module access to instance name	InTheMiddle	1	3842	Dec 27^th, 2013, 1:38pm By: Andrew Beckett
Understanding resistor usage	GregS	1	4097	Sep 12^th, 2013, 4:32am By: boe
cds_thru	Ken Kundert	1	5390	Apr 7^th, 2013, 6:35am By: Peter Grove
gmin value for functional verifications	Dushyant Juneja	14	16150	Feb 6^th, 2013, 8:43pm By: Dushyant Juneja
Cross view checking vs. linked file	BillH	0	3219	Jan 21^st, 2013, 12:18pm By: BillH
Analog �Verification	neetirajgor	4	9132	Aug 9^th, 2012, 12:28am By: MehaboobAli
Moved: Corner Simulations without ADE-XL - Started by: Berti This Topic has been moved to Circuit Simulators by Forum Administrator
Oversampling CDR	kinshuk	0	3787	Mar 26^th, 2012, 6:36am By: kinshuk
analog circuits synthesis tools	koma	8	13369	Dec 18^th, 2011, 5:18pm By: loose-electron
Who should be the chip level verification engineer(digital+analog chip)?	sunnylvee	9	20671	Oct 27^th, 2011, 5:02pm By: loose-electron

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