Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Veriloga Auto Parser not working when code saved!	gte558w	0	1209	Jan 8^th, 2016, 9:44am By: gte558w
How to write script in VCS-MX?	Gp	0	1388	Jan 8^th, 2016, 3:01am By: Gp
VAMS clock period monitor- Help!	Rosh	4	3418	Jul 15^th, 2015, 2:15am By: Rosh
Ideal voltage source in spectre	rampat	3	7978	May 13^th, 2015, 8:31am By: Geoffrey_Coram
avoiding singular matrix and zero diagonal messages	suam	1	2867	Nov 9^th, 2014, 3:45pm By: Ken Kundert
Linear Regulator test bench	amruta	7	5629	Nov 6^th, 2014, 10:51am By: amruta
Module access to instance name	InTheMiddle	1	3243	Dec 27^th, 2013, 1:38pm By: Andrew Beckett
Understanding resistor usage	GregS	1	3503	Sep 12^th, 2013, 4:32am By: boe
cds_thru	Ken Kundert	1	4749	Apr 7^th, 2013, 6:35am By: Peter Grove
gmin value for functional verifications	Dushyant Juneja	14	13505	Feb 6^th, 2013, 8:43pm By: Dushyant Juneja
Cross view checking vs. linked file	BillH	0	2835	Jan 21^st, 2013, 12:18pm By: BillH
Analog �Verification	neetirajgor	4	7971	Aug 9^th, 2012, 12:28am By: MehaboobAli
Moved: Corner Simulations without ADE-XL - Started by: Berti This Topic has been moved to Circuit Simulators by Forum Administrator
Oversampling CDR	kinshuk	0	3318	Mar 26^th, 2012, 6:36am By: kinshuk
analog circuits synthesis tools	koma	8	11567	Dec 18^th, 2011, 5:18pm By: loose-electron
Who should be the chip level verification engineer(digital+analog chip)?	sunnylvee	9	18563	Oct 27^th, 2011, 5:02pm By: loose-electron
Linter for VHDL-AMS, Verilog-AMS	hakke	0	2863	Sep 5^th, 2011, 3:22am By: hakke
ams simulator has very limited analog (solver) capability	ywguo	2	5240	Jul 5^th, 2011, 12:23am By: Ken Kundert
Moved: Migrating from cadence IC5 to IC6.1.4 - Started by: MarcoC This Topic has been moved to Entry Tools by Ken Kundert
Question about Offset-Simulation of comparators	mate	2	4561	Dec 18^th, 2010, 8:38am By: AnalogDE

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