The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 19th, 2019, 10:15pm
Pages: 1
Send Topic Print
Question about verilog-A delay function (Read 5991 times)
asifqaiyum
New Member
*
Offline



Posts: 4

Question about verilog-A delay function
Feb 16th, 2016, 8:15am
 
Dear All:

I have three questions regarding the verilog-A delay function.

// VerilogA example
absdelay(V(node1,node2), DEL_N1toN2);

--> continuous delays the signal between node1 and node2 by the amount "DEL_N1toN2".

1.      What is the tolerance of this delay function? If I give DEL_N1toN2=50us, how does the actual delay look like? (50us +- some tolerance???)
2.      I get warning messages in spectre simulations:
   WARNING (CMI-2080): Saved timepoints in delay buffer have exceeded `32768'. Simulation may take too many timesteps.

How does the warning affect the accuracy of the simulation/delay itself/the signal to be delayed?

3. From where does "32768" come? This is the max of 16-bit signed integer.

I run the transient simulation with the following setting:
conservative, reltol=1e-5, gmin=1e-15

Thanks and Best Regards,
Asif
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2161
Silicon Valley
Re: Question about verilog-A delay function
Reply #1 - Feb 16th, 2016, 1:54pm
 
Quote:
conservative, reltol=1e-5, gmin=1e-15
Why in the world to you think you need to use such tight tolerances?

32768 is an arbitrary limit. Exceeding it should not limit your accuracy, they are just saying that your delay line is saving up a lot of points before they can be used, which is unusual.

There are no tolerances associated with the delay line.

Why are using an analog delay line? It is an expensive feature that is tough to simulate and the interpolation that is needed at the output degrades the accuracy of the simulation. My experience is that most people that try to use this feature are trying to delay digital signals, and in that case you should be using a transition function.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
asifqaiyum
New Member
*
Offline



Posts: 4

Re: Question about verilog-A delay function
Reply #2 - Feb 17th, 2016, 1:24am
 
Ken,

thank you so much for your reply.

Let me explain you what I am doing. I am simulating analog front end (transistor level) which excites the external transducer (verilogA model with channel delay) and receives the input signal.

I am interested in the drift of the input signal over temperature with respect to time, i.e. run two simulations (at room and high temp) and compare the received signal, how much the received signals shift in time (done in matlab).

Signal shift in time needs to be resolved down to ps resolution. I have tried different tolerance settings, and reltol=1e-5 (or smaller) gives the same result.

Circuit is designed in very low leakage process, so I generally use gmin=1e-15.

By the way, I have also asked Cadence guys, but still waiting for the reply Sad Your reply is faster Smiley

Thanks once again,
A.

Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2161
Silicon Valley
Re: Question about verilog-A delay function
Reply #3 - Feb 17th, 2016, 1:20pm
 
Quote:
Signal shift in time needs to be resolved down to ps resolution.


Is there some event that you are using when measuring signal shift, say a threshold crossing perhaps? If so, it is generally much more efficient to use cross and perhaps last_crossing to resolve the event accurately rather than using tight tolerances everywhere.

You still do not say why you are using absdelay().

-Ken
Back to top
 
 
View Profile WWW   IP Logged
asifqaiyum
New Member
*
Offline



Posts: 4

Re: Question about verilog-A delay function
Reply #4 - Feb 18th, 2016, 1:20am
 
Hi Ken,

signal shift is measured through matlab script. I run the spectre simulations only to get the two received signals and then export it in .csv file.

As I have mentioned previously, analog front end excites the external transducer (actually RLC model) and the transducer produces damped sin waves which is further delayed. So that's why absdelay() is used.

The delayed signals are the received signals which I export to matlab for computing signal shift.

Regards,
A.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2161
Silicon Valley
Re: Question about verilog-A delay function
Reply #5 - Feb 18th, 2016, 11:29am
 
absdelay() implements transport delay, which is unusual except at very high frequencies. This is the delay of a transmission line. Are you actually modeling a transmission line? If not, you probably do not need absdelay(). A damped sinusoid suggests the delay of an LCR.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
asifqaiyum
New Member
*
Offline



Posts: 4

Re: Question about verilog-A delay function
Reply #6 - Feb 19th, 2016, 4:01am
 
absdelay() models the delay of the channel.

The channel is modeled (in verilogA) as two port network (actually RLC) with attenuation factor.

Regards,
A.

Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2019 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.