Andrew Beckett
Senior Fellow
    
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Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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I don't think there's any support for generating pure verilog. There's support for VerilogAMS and SystemVerilog, but of course if you're not using any of Verilog-AMS or SystemVerilog features, you could take the code and use elsewhere.
However, the goal of the tool is primarily for generating real number models.
Regards,
Andrew.
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