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Verilog AMS co simulation with SV (Read 4840 times)
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Posts: 13
Verilog AMS co simulation with SV
Feb 24th, 2015, 4:40am
Hi all,

I wanted to simulate the verilog ams code with testbench as SV/UVM.

I face some problem but when I simulate with spice and SV its working fine.

Do I need to write amsd{
block for running verilog -AMS with SV.

I am using cadence simulator and running the simulation from command line.

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Posts: 67

Re: Verilog AMS co simulation with SV
Reply #1 - Jan 18th, 2017, 8:04am

sv and ams cannot co-exist. You have to remove -sv switch from the irun option if you have used it.

Then it should be compiling fine.

Thank you.

Kind regards,
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Andrew Beckett
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Re: Verilog AMS co simulation with SV
Reply #2 - Jan 20th, 2017, 9:21am
Note that this last reply was a bit misleading. Verilog-AMS and SystemVerilog can coexist. You should however use the file suffix to determine whether it is compiling Verilog-AMS or SystemVerilog rather than forcing it via a command line option (which would indeed cause a problem). It's not clear whether that was the problem the original poster faced - it was an elderly posting...


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