Hi all,

I wanted to simulate the verilog ams code with testbench as SV/UVM.

I face some problem but when I simulate with spice and SV its working fine.

Do I need to write amsd{
}
block for running verilog -AMS with SV.

I am using cadence simulator and running the simulation from command line.

Thanks

Note that this last reply was a bit misleading. Verilog-AMS and SystemVerilog can coexist. You should however use the file suffix to determine whether it is compiling Verilog-AMS or SystemVerilog rather than forcing it via a command line option (which would indeed cause a problem). It's not clear whether that was the problem the original poster faced - it was an elderly posting...

Regards,

Andrew