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Linear Regulator test bench (Read 1946 times)
amruta
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Linear Regulator test bench
Oct 28th, 2014, 8:49am
 
Hello ,

I am trying to write a verilog-AMS code for DC step function which will act as a input to the Linear Regulator. Does anyone have an example code for this?

Thanks.
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boe
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Re: Linear Regulator test bench
Reply #1 - Oct 29th, 2014, 3:09am
 
Amruta,
I recommend you use a "transition filter" for this.
- B O E
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amruta
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Re: Linear Regulator test bench
Reply #2 - Oct 29th, 2014, 8:06am
 
Hello BOE,
Thank you.
Do you have any recommendation on how to construct a a piecewise linear source for the input of the regulator? Slew rate is 3V/10US.

Thanks a lot.
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boe
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Re: Linear Regulator test bench
Reply #3 - Oct 30th, 2014, 4:59am
 
Amruta,
you could combine a slew filter and a transition filter: Code:
slew(transition(Vsignal, tdelay, trisefall_min), slew_max) 

- B O E
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Ken Kundert
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Re: Linear Regulator test bench
Reply #4 - Oct 30th, 2014, 12:34pm
 
Wrapping slew around transition is redundant and you should not do it.

To do what you want you need code that looks something like this:

Code:
real Vraw;
initial begin
   ...
   for (Vraw=1.5; Vraw < 18.5; Vraw = Vraw + 0.5) begin
	 #(10u);
	 fails = abs(V(out) - Vexpected) < 25m;
	 strobe("%s: V(out) = %fV, expected = %fV", fails ? "FAILED" : "Passed", V(out), Vexpected);
   end
   ...
end
analog begin
   ...
   V(raw) <+ transition(Vraw, 0, 1u);
   ...
end 


-Ken
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amruta
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Re: Linear Regulator test bench
Reply #5 - Oct 31st, 2014, 8:32am
 
Ken,
I tried your method, but I was not getting the voltage to rise from 0 to 3V. Rather it was staying steady at 3V right from the start. What can I do to ramp this voltage from 0 to 3V with a slew rate of 0.3V/us?

initial begin
for (Vraw = 0; Vraw <2.9;Vraw = Vraw+ 0.3)begin
$strobe("Vraw=%f. \n", Vraw);
#(1u);
end
end
analog begin                
                               
                       
//V(piecewise_voltage_source)<+(values[i+1] - values[i]) * ($abstime - times[i])/(times[i+1] - times[i]) + values[i];
V(piecewise_voltage_source) <+ transition ( Vraw,0,50u);
V(vsrc)<+V(piecewise_voltage_source);
I(current_in_out) <+ V(vin, vout)/rdson;
x=I(vsrc,vin);
$strobe("x=%f. \n", I(vsrc,vin));
end
endmodule
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Ken Kundert
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Re: Linear Regulator test bench
Reply #6 - Oct 31st, 2014, 1:32pm
 
Your code is quite different from mine. Perhaps if you used my code it would work?

-Ken
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amruta
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Re: Linear Regulator test bench
Reply #7 - Nov 6th, 2014, 10:51am
 
Ken,

Thank you Smiley. I used your code..it works now.

Regards, Amruta
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