Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
How to parametrize input bits of a DAC in Verilog A code	Andrea8888	1	141	Oct 6^th, 2023, 10:22am By: Ken Kundert
VerilogA random DC value	Horror Vacui	3	327	Sep 11^th, 2023, 8:02pm By: Ken Kundert
How to create a verilog-A testbench to run a sweep of all input pins	avlsi	7	708	Aug 21^st, 2023, 11:43pm By: Ken Kundert
ADE L Stuck due to timescale definition	Zaidi	2	411	Mar 27^th, 2023, 5:04am By: Zaidi
How to generate pulse with different amplitude within same transient analysis.	Shah	5	764	Aug 31^st, 2022, 11:57am By: Ken Kundert
Proper modelling of a current source in verilogAMS.	edstrom	3	2176	Jun 28^th, 2021, 1:20am By: Horror Vacui
Query on a verilogA based pulse generation using a timer blocks.	subtr	4	936	Jun 14^th, 2021, 11:32pm By: subtr
What is the PSD of noise generated using rdist_normal function?	subtr	11	287	Aug 13^th, 2019, 11:38am By: subtr
Binary bus evaluation in CASE statement for VerilogA	Guile	3	1262	Jul 11^th, 2019, 7:18am By: Ken Kundert
Help with a verilog-A code	anaspire	1	2343	Jul 31^st, 2018, 11:23am By: Ken Kundert
Fast transient for analog mixed signal verification	deba	2	2032	Jul 28^th, 2018, 2:18am By: deba
Moved: VCO Simulink simulation - Started by: yngwie87 This Topic has been moved to System Simulators by Ken Kundert
Issue with Cadence analog value fetch functions	sgh2050	1	97	Dec 21^st, 2017, 7:43am By: Andrew Beckett
Assertions inside Connect Modules	sgh2050	1	83	Nov 30^th, 2017, 1:12am By: nischaybm
PNOISE with a VerilogA oscillator	Horror Vacui	3	3618	Sep 11^th, 2017, 5:07pm By: cheap_salary
creating compile time define switch in .scs file	AMS_ei	5	4718	Jun 3^rd, 2017, 12:37am By: Andrew Beckett
Test schematic using verilogams testbench	edstrom	1	2375	May 20^th, 2017, 12:02am By: AMS_ei
use of $dumpvar	Designe_IT	1	84	May 1^st, 2017, 9:52am By: AMS_ei
Syntax for vsource ramp generator	Rosh	1	1002	Apr 25^th, 2017, 11:01am By: AMS_ei
Schematic Model Generator (SMG) tool	Lala878	3	3824	Mar 8^th, 2017, 9:54pm By: Andrew Beckett

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