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The Designer's Guide Community Forum › Analog Verification › Analog Functional Verification › How to parametrize input bits of a DAC in Verilog A code
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How to parametrize input bits of a DAC in Verilog A code (Read 162 times)
Andrea8888
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How to parametrize input bits of a DAC in Verilog A code
Oct 06th, 2023, 1:10am  
Hi All,

as written in the subject, in case i want to leave the number of bits as parameter that user can choose in every run without changing the code ..: how to do it?
Which is the syntax to leave inputs / outputs of an istance as parameter?

Thanks in advance for the help
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Ken Kundert
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Re: How to parametrize input bits of a DAC in Verilog A code
Reply #1 - Oct 6th, 2023, 10:22am  
Take a look at https://designers-guide.org/verilog-ams/functional-blocks/data-converter/convert...
er-lrm.vams

However, be aware that you cannot use such a model in a Cadence schematic.  Schematics do not allow the number of lines in a wire to be variable.
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