Designer’s Guide Community

Pages: 1 2 3 ... 20

Subject	Started by	Replies	Views	Last post
Phase noise and SFDR measurement of a Digital to Frequency Converter	seriuswhite	2	109	Aug 22^nd, 2020, 10:36am By: seriuswhite
jitter measurement for phase domain model PLL	rezarmzn	3	105	Aug 20^th, 2020, 10:47am By: Ken Kundert
phase.vams	as_rf	3	348	Mar 1^st, 2020, 2:31am By: Andrew Beckett
PLL phase noise results	as_rf	0	156	Feb 28^th, 2020, 10:59am By: as_rf
VCO Phase Noise Modeling using Verilog-A, Verilog-AMS	repah	1	175	Feb 19^th, 2020, 2:53pm By: Ken Kundert
determining jitter contribution from individual PLL block	thewirehead	0	150	Feb 1^st, 2020, 1:32am By: thewirehead
phase.vams file for Predicting the Phase Noise and Jitter of PLL, by Ken	thewirehead	2	297	Nov 20^th, 2019, 5:56pm By: thewirehead
Phase Noise measurement for PLL in closed Loop	thewirehead	2	286	Nov 10^th, 2019, 9:12pm By: thewirehead
Phase noise measurement using E5052B	deba	1	409	Sep 18^th, 2019, 5:01am By: Horror Vacui
divider pm jitter measurement example?	newmedia	2	312	Aug 6^th, 2019, 2:14pm By: newmedia
clock divider - jitter	trond	13	897	Jun 25^th, 2019, 7:44am By: Anex
Is "phase jitter" short term jitter or long term accumulated?	Homer	1	494	Apr 15^th, 2019, 3:40am By: subtr
Reference effect on PLL PN	Farzaneh	3	1230	Nov 3^rd, 2018, 11:38pm By: Ken Kundert
the phase discipline fails following the verilogA PLL noise/jitter	qingyinnj	1	835	Oct 21^st, 2018, 11:01am By: Andrew Beckett
Jitter from specreRF pnoise	dkumar	1	981	Aug 16^th, 2018, 3:35am By: deba
ISI jitter due to supply noise	iVenky	0	801	May 20^th, 2018, 7:53pm By: iVenky
questions in simulating jitter performance of crystal osc +squaring buffer	specialest	2	4306	Apr 7^th, 2018, 11:16am By: dentex
Spectrum analyzer spurs measurement	iVenky	1	1178	Feb 28^th, 2018, 8:44pm By: deba
Spectre .pnoise type sources vs pmjitter	deba	0	883	Feb 1^st, 2018, 4:45am By: deba
question on phase-domain phase detector noise model	tulip	3	1670	Jan 26^th, 2018, 12:46am By: tulip

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