I want to model a complete PLL behaviourally and use Verilog-A and Verilog-AMS.

My VCO has a known KVCO and a known Phase Noise at a 1MHz offset (say 130dbc/hz).  I also know the VCO noise floor (say -140dbc/hz) and that it has a 1/f^3 dependence elsewhere.

I am using Predicting the Phase Noise of PLL-Based Frequency Synthesizers as a guide.

From Listing 3 and Listing 4 in this document, especially Listing 4, I can remove the 1/f^2 dependence but how do I add in the noise floor of the VCO.

Thank you.

If you can assume the noise is dominated by white noise, then you can actually make the vco model in verilogAMS by deriving period jitter from it. Now given that the noise at an offset is known, the curve is completely defined in all the points or in other words you can find out the N=H(f) of the noise. Assuming that you need the period jitter, multiply it by a (1-zinv) filter and integrate the noise. This is the sigma of each period. Now you find a random number in your code based on this sigma and pass it to the oscillator. It will generate an integrated noise which corresponds to the PSD of your actual oscillator. Da Dalt's book on understanding jitter has details on retrieving period jitter from spot noise of purely 1/f^2 noise.

You can even model flicker noise by using multirate filters to create 10dB/decade which is explained in Staszewski's book. But it can be a next step.