Hi Jeffyan,

I think that is reasonable in the link

http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt. I quote it here.

Scenario 1 is the percentage of jitter to period, while the jitter is random.

Scenario 2 is the percentage of jitter to period, while the jitter is deterministic.

Scenario 3 is the absolute jitter, while the jitter is random.

Scenario 4 is the absolute jitter, while the jitter is deterministic.

**Quote:**Q: What are the effects of dividing the VCO output by 2 on output jitter?

A: It depends on your assumptions although in general it doesn't make much

difference.

Analysis:

---------

When comparing the effects of dividing the VCO by 1 or 2

on clock jitter, to first-order we can ignore the PLL's feedback

loop. Why? VCO jitter is primarily determined by high-frequency

power-supply noise and other forces that act on the VCO much faster

than the feedback loop can respond.

There are four scenaria to consider:

Cases #1 and #2 are more realistic in that VCO jitter tends to decrease with

increasing VCO frequency. To first order, you can assume that VCO jitter

remains a constant percentage of the VCO period. This is the assumption

used in the first two scenaria.

1) If VCO jitter is a constant percentage of period (smaller absolute

jitter at high frequencies) and random, then jit(div2) = sqrt(2)/2 * jit(div1).

Dividing by 2 is better by 30%.

Note that the sqrt(2) function accounts for how we add two statistically independent error functions.

2) If VCO jitter is a constant percentage of period and deterministic,

then jit(div2) = jit(div1). Div-by-2 is the same as div-by-1.

The assumption is that the worst-case noise pattern persists for at least

2 VCO cycles, and so both phases of the divided clock "see" the noise.

3) If VCO jitter magnitude is constant with changing frequency and Gaussian

(think thermal noise and/or random VDD noise), then jit(div2) = sqrt(2) * jit(div1).

In this case, dividing by 2 is 40% worse.

4) If VCO jitter is constant and deterministic (think pattern-dependent VDD noise),

then jit(div2) = 2 * jit(div1). In this case, dividing by 2 is 100% worse.

In the end, the decision whether or not to divide the VCO by 2 is going to be driven

by duty cycle requirements, VCO min/max speed, VCO frequency range over which

power-supply noise is acceptable, PVT-related variations, divider logic

complexity, availability of power-supply filter, etc. The "academic" exercise

above shows merely that there is NOT a strong "a priori" argument to dividing

the the VCO clock by 2. Sometimes it helps, sometimes it hurts.

Best wishes,

Yawei