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clock divider - jitter (Read 20854 times)
trond
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clock divider - jitter
Jun 17th, 2007, 11:52pm
 
When dividing a system clock with a specified jitter, J, down by a factor of M, does the slower clock have the same jitter as the fast system clock or is it divided by M as well? I think the jitter is the same but might overlook something. For example jitter to period will change?

For example, I am sampling a rectified frequency modulated signal. Thus I am introducing an error in each zero-crossing. When the clock has jitter, all I am doing as either adding or subtracting a little bit of the error introduced by the jitter-free clock.
Now when decreasing the frequency of the clock, will the error due to jitter still be the same?

Any comments are welcome.

Cheers


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imtired
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Re: clock divider - jitter
Reply #1 - Jun 25th, 2007, 2:12pm
 
I'll take a stab at this...

When you divide the clock, I believe that the absolute random jitter will be that of the clock plus the divider residual jitter.  (Otherwise, where else is the jitter introduced from?)  If you have some periodic jitter, then maybe the jitter characteristics may change after going through the divider.

In terms of UI and L(f), the jitter should decrease (assuming the divider noise is low compared to the clock noise), because of what you already said, that is the period increases, while the amount of displacement of the clock edge from its ideal edge (i.e. absolute jitter) stays roughly the same.  This is a consequence of all signals within the divider circuit being dependent on the input clock edge.

You can also think of it as sampling the clock edges at a lower rate.  The samples that you end up with are roughly the same as the input (and slightly corrupted by the divider circuitry), except they occur less frequently in time (longer period).

I hope that helps.

Robert
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trond
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Re: clock divider - jitter
Reply #2 - Jun 26th, 2007, 11:02pm
 
Thanks for the response.

Out of curiosity. I was playing around with the frequency divider on the VerilogA/AMS page and was increasing the jitter to see the effects. At some point it happened that one of the jitter free edges was delayed and the consecutive edge was advanced such that an overlap occurred, and as a result, the jittered clock was missing an edge.

Does such a thing ever happen in real life, especially at high clock frequencies?
Also, are there schemes which divide a high clock and also reduce the absolute jitter?

Thanks
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imtired
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Re: clock divider - jitter
Reply #3 - Jun 27th, 2007, 11:41am
 
In my experience, the divider noise is usually at least 2 orders of magnitude less than the period, which means practically you would never see such an event where one edge skips over another because of jitter.  I've experience with SiGe dividers up to 40GHz input frequencies, that's 25 psec period, while the residual jitter is lower than what I can measure on Agilent's DCA, which is ~200-300 fsec RMS.  And there are probably a handful publications on higher frequency dividers using CMOS.

As for decreasing the absolute jitter, I've never actually considered anything like that before.  But I could imagine a couple of ways to decrease the jitter of a signal in general.  One way would be to use a re-timer at the output with a cleaner synchronized clock doing the re-timing.  Or another way is to use a clean-up PLL either before or after the divider.
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trond
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Re: clock divider - jitter
Reply #4 - Jul 3rd, 2007, 4:12am
 
Thanks for your feedback imtired. You were very helpful.

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buckaroo
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Re: clock divider - jitter
Reply #5 - Aug 9th, 2007, 6:54pm
 
yes, the jitter is the same, however, the period is longer, the phase noise is better, u can find the simple relation in SpectreRF_VCO533AN.pdf, which u can get in cadence homepage
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JPR75
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Re: clock divider - jitter
Reply #6 - Aug 21st, 2007, 1:32pm
 
Sometime people get confused because when you convert from phase noise to jitter, you divide by the frequency...
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imtired
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Re: clock divider - jitter
Reply #7 - Nov 15th, 2007, 10:33am
 
Yes the phase noise is better (in most cases by 6dB per division), but you really have to consider what the specific application is calling for.  Sometimes phase noise is the appropriate performance criteria, while other times integrated jitter is more appropriate.  Depends on what you're trying to do.

And another thing, sometimes people can get confused by just looking at phase noise alone without really considering what's going on.  You might think that because the phase noise improves by 6dB that the actual jitter has improved as well.  But if you look at absolute jitter, then the jitter really hasn't decreased at all, in fact it probably is a tiny bit worse after going through the divider, due to residual divider noise.  But if you look in terms of UI, then yes the jitter would have less UI, precisely because of what buckaroo was saying (the period doubles, but absolute jitter stays the same).  
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bart
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Re: clock divider - jitter
Reply #8 - Jan 16th, 2008, 6:16am
 
Hi,

I understand, that you're talking about synchronous dividers... in which the output clock is synchronized with input clock. In case of asynchronous divider (like a simple flip-flops chain) jitter would increase by sqrt(N). Am I right?

Regards,
Bart
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buckaroo
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Re: clock divider - jitter
Reply #9 - Feb 27th, 2008, 10:57pm
 
yes, you are right

bart wrote on Jan 16th, 2008, 6:16am:
Hi,

I understand, that you're talking about synchronous dividers... in which the output clock is synchronized with input clock. In case of asynchronous divider (like a simple flip-flops chain) jitter would increase by sqrt(N). Am I right?

Regards,
Bart

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jeffyan
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Re: clock divider - jitter
Reply #10 - Mar 3rd, 2008, 9:39pm
 
hi all,
have you visited the following page:
http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt.
things gets more complicated. i don't really understand what the jitter specifed in above link.
let's have a discussion.
jeff
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ywguo
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Re: clock divider - jitter
Reply #11 - Apr 14th, 2008, 12:34am
 
Hi Jeffyan,

I think that is reasonable in the link http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt.  I quote it here.

Scenario 1 is the percentage of jitter to period, while the jitter is random.
Scenario 2 is the percentage of jitter to period, while the jitter is deterministic.
Scenario 3 is the absolute jitter, while the jitter is random.
Scenario 4 is the absolute jitter, while the jitter is deterministic.

Quote:
Q: What are the effects of dividing the VCO output by 2 on output jitter?

A: It depends on your assumptions although in general it doesn't make much
difference.

Analysis:
---------
When comparing the effects of dividing the VCO by 1 or 2
on clock jitter, to first-order we can ignore the PLL's feedback
loop. Why? VCO jitter is primarily determined by high-frequency
power-supply noise and other forces that act on the VCO much faster
than the feedback loop can respond.

There are four scenaria to consider:

Cases #1 and #2 are more realistic in that VCO jitter tends to decrease with
increasing VCO frequency. To first order, you can assume that VCO jitter
remains a constant percentage of the VCO period. This is the assumption
used in the first two scenaria.

1) If VCO jitter is a constant percentage of period (smaller absolute
jitter at high frequencies) and random, then jit(div2) = sqrt(2)/2 * jit(div1).
Dividing by 2 is better by 30%.

Note that the sqrt(2) function accounts for how we add two statistically independent error functions.


2) If VCO jitter is a constant percentage of period and deterministic,
then jit(div2) = jit(div1). Div-by-2 is the same as div-by-1.

The assumption is that the worst-case noise pattern persists for at least
2 VCO cycles, and so both phases of the divided clock "see" the noise.


3) If VCO jitter magnitude is constant with changing frequency and Gaussian
(think thermal noise and/or random VDD noise), then jit(div2) = sqrt(2) * jit(div1).
In this case, dividing by 2 is 40% worse.


4) If VCO jitter is constant and deterministic (think pattern-dependent VDD noise),
then jit(div2) = 2 * jit(div1). In this case, dividing by 2 is 100% worse.

In the end, the decision whether or not to divide the VCO by 2 is going to be driven
by duty cycle requirements, VCO min/max speed, VCO frequency range over which
power-supply noise is acceptable, PVT-related variations, divider logic
complexity, availability of power-supply filter, etc. The "academic" exercise
above shows merely that there is NOT a strong "a priori" argument to dividing
the the VCO clock by 2. Sometimes it helps, sometimes it hurts.




Best wishes,
Yawei
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wen.sun
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Re: clock divider - jitter
Reply #12 - May 7th, 2008, 10:44pm
 
i have a question

when converting the phase noise to jitter, for example, if the oscillation frequency is 800MHz, the phase noise is integrated from 10kHz to 20MHz,  is the jitter a long term jitter(800MHz/10kHz=80000 cycle)?

according to the period jitter(one cycle), how much frequency offset should be integreated?
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Anex
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Re: clock divider - jitter
Reply #13 - Jun 25th, 2019, 7:44am
 
Hi all,

I didn't quite understand how Scenario 3 works out. Could someone explain with some equations? Where does the sqrt(2) come from? What two random variables are being added here?

ywguo wrote on Apr 14th, 2008, 12:34am:
Hi Jeffyan,

I think that is reasonable in the link http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt.  I quote it here.


Scenario 3 is the absolute jitter, while the jitter is random.

Quote:
Q: What are the effects of dividing the VCO output by 2 on output jitter?

A: It depends on your assumptions although in general it doesn't make much
difference.

Analysis:
---------



3) If VCO jitter magnitude is constant with changing frequency and Gaussian
(think thermal noise and/or random VDD noise), then jit(div2) = sqrt(2) * jit(div1).
In this case, dividing by 2 is 40% worse.





Best wishes,
Yawei

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