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Feb 27th, 2020, 10:56pm
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determining jitter contribution from individual PLL block (Read 69 times)
thewirehead
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determining jitter contribution from individual PLL block
Feb 01st, 2020, 1:32am
 
Hey there,
I'm in the middle of 2.4GHz Integer PLL, Reference clock is 150MHz and Feed back divider is 16. Currently I'm getting rms period jitter of 1.2ps (please let me know if rms of period jitter plot (from virtuoso calculator) is good enough).

My question is how do i determine the jitter contribution from individual PLL block, such as per divider, post divider, feedback divider, LPF, charge pump and VCO (VCO I usually run PSS PNOISE and see Jee/Jcc)? this is my biggest concern, please help.

Please help me answering both the questions. Thanks a lot in advance

cheers  :) Smiley

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