Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
what is the usage of the port in the fpga?	liletian	0	239	Aug 28^th, 2018, 11:14am By: liletian
how to re-run irun simulation?	liletian	2	1810	Aug 27^th, 2018, 2:01pm By: liletian
rc synthesize problem	liletian	0	131	Aug 23^rd, 2018, 11:08am By: liletian
how to save simulation data and re-view the data again and again?	liletian	1	1593	Aug 20^th, 2018, 2:20am By: deba
how to reverse the signal order when create bus in irun results?	liletian	1	181	Aug 20^th, 2018, 2:20am By: deba
how to include a module in another module?	liletian	1	1979	Aug 10^th, 2018, 4:50am By: Andrew Beckett
how to print integer in the verilog module	liletian	1	1374	Aug 9^th, 2018, 4:26am By: Andrew Beckett
Issue of unrecognized system task or function: $cdn_ahb_access	TDG_40	1	180	Dec 21^st, 2017, 7:21am By: Andrew Beckett
Validation of $write() for encrypted Verilog-A modules in Cadence Tool	cheap_salary	3	4308	Aug 2^nd, 2017, 9:14pm By: Andrew Beckett
IRUN user manual	l.malane	1	234	Mar 20^th, 2017, 8:16am By: Andrew Beckett
Unencryption of encrypted veriloga code in Cadence Tools	cheap_salary	1	214	Dec 29^th, 2016, 2:23am By: Andrew Beckett
how to use arm M0 core to implemented micro-controller?	liletian	0	136	Sep 1^st, 2015, 12:10pm By: liletian
OSSHNL ERROR 514 and 287	peteK	4	386	Nov 5^th, 2014, 10:13pm By: peteK
Math functions in Cadence NCVerilog	cheap_salary	9	623	Sep 26^th, 2014, 2:37am By: boe
modelsim de 6.5 installation	kamela	0	152	Dec 24^th, 2013, 6:57am By: kamela
Unknown logical value in AMS simulation.	mepr428	2	6147	Jul 3^rd, 2012, 1:07pm By: mepr428
how to use the verilog views of many cells in one single file	xuedashun	0	109	Jan 26^th, 2012, 9:34am By: xuedashun
What's the difference for irun options between "-y" and "-incdir"	paopaochong	1	163	Dec 12^th, 2011, 10:27pm By: En7gizer4143LL
IBIS AMI model	haykp	1	8796	Feb 23^rd, 2011, 6:25am By: Frank Wiedmann
Gate level netlist to RTL	rajdeep	4	12616	Jan 11^th, 2011, 2:59am By: Andrew Beckett

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