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Math functions in Cadence NCVerilog (Read 14739 times)
cheap_salary
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Math functions in Cadence NCVerilog
Sep 24th, 2014, 3:51am
 
I can use following Conversion Functions in Cadence NCverilog.

$bitstoreal(), $realtobits()
$itor(), $rtoi
$signed(), $unsigned()

However I can not use following Math functions in Cadence NCVerilog.

$acos(), $acosh(), $asin(), $asinh(), $atan(), $atan2(), $atanh()
$clog2(), $ceil(), $cos(), $cosh()
$exp(), $floor(), $hypot(), $ln(), $log10()
$pow(), $sin(), $sinh(), $sqrt(), $tan(), $tanh()

I tried option of ncverilog command, "+ncams" and "+sv".
However both were not effective.

Are Math functions unavailable in Cadence NCVerilog ?
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boe
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Re: Math functions in Cadence NCVerilog
Reply #1 - Sep 24th, 2014, 4:14am
 
Hi Cheap_salary,
the math functions you list are System-Verilog; in Verilog-AMS they have a different Syntax (no $), while they are not available in standard Verilog.
So, if you want to use them, you need System-Verilog or Verilog-AMS code using the appropriate syntax - and then they should work.
- B O E
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cheap_salary
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Re: Math functions in Cadence NCVerilog
Reply #2 - Sep 24th, 2014, 4:32am
 
Thanks for response.

boe wrote on Sep 24th, 2014, 4:14am:
in Verilog-AMS they have a different Syntax (no $)
Of course, I know.

boe wrote on Sep 24th, 2014, 4:14am:
So, if you want to use them, you need System-Verilog
I think "+sv" option for "ncverilog" command make System-Verilog Keyword enable.
However even if I set "+sv" option, situations don't change.

On the other hand, I can use Math-Functions in Icarus-Veriog with -g2001 (IEEE1364-2001).
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boe
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Re: Math functions in Cadence NCVerilog
Reply #3 - Sep 24th, 2014, 5:18am
 
Cheap_salary,
I have never needed these functions in (System-)Verilog myself, so I am not a specialist for this - but I know that they work in Verilog-AMS (analog context).
Using ncverilog, I would use <file>.sv for System-Verilog code, which then should accept the meth functions (Cadence System-Verilog docs do not indicate otherwise).
- B O E
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Re: Math functions in Cadence NCVerilog
Reply #4 - Sep 24th, 2014, 5:57am
 
boe wrote on Sep 24th, 2014, 5:18am:
but I know that they work in Verilog-AMS (analog context).
I don't want to exhaust MMSIM License for AMS option.
And available system tasks are different between Verilog-D and Verilog-AMS.
http://www.designers-guide.org/Forum/YaBB.pl?num=1193119921/0#0

Verilog-A is a subset of Verilog-AMS, but Verilog-D(1995, 2001, 2005) is not a subset of Verilog-AMS.

boe wrote on Sep 24th, 2014, 5:18am:
Using ncverilog, I would use <file>.sv for System-Verilog code
I don't think a file extension has any meaning for Cadence NCsim.
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Re: Math functions in Cadence NCVerilog
Reply #5 - Sep 24th, 2014, 6:16am
 
cheap_salary wrote on Sep 24th, 2014, 5:57am:
.. I don't want to exhaust MMSIM License for AMS option.
And available system tasks are different between Verilog-D and Verilog-AMS.
http://www.designers-guide.org/Forum/YaBB.pl?num=1193119921/0#0

Verilog-A is a subset of Verilog-AMS, but Verilog-D(1995, 2001, 2005) is not a subset of Verilog-AMS.
According to V-AMS LRM 2.3.1 "Verilog-AMS HDL consists of the complete IEEE std 1364-2005 Verilog HDL specification, ...", but of course the implementations may NOT provide this.

Quote:
boe wrote on Sep 24th, 2014, 5:18am:
Using ncverilog, I would use <file>.sv for System-Verilog code
I don't think a file extension has any meaning for Cadence NCsim.
It seems I have used irun flow too often recently (but how does ncverilog determine file language...?).
- B O E
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Re: Math functions in Cadence NCVerilog
Reply #6 - Sep 25th, 2014, 1:45am
 
Cheap_salary,
My short test case
Code:
module test();
  initial begin
    $display($sin(0), " ", $cos(0), " ", $sin(1.57), " ", $cos(1.57));
    $finish;
  end
endmodule 

works fine.
- B O E
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Re: Math functions in Cadence NCVerilog
Reply #7 - Sep 25th, 2014, 7:15am
 
The followings are results of "Icarus Verilog Preprocessor version 0.9.7"

Quote:
module test;
real pi1, pi2;

initial begin
  pi1 = $acos( -1.0);
  $display( "pi1=%f, $sin(pi1/2)=%f, $cos(pi1)=%f",
            pi1, $sin(pi1 / 2), $cos(pi1) );

  pi2 = acos( -1.0);
  $display( "pi2=%f, sin(pi2/2)=%f, cos(pi2)=%f",
            pi2, sin(pi2 / 2), cos(pi2) );
end //initial

endmodule


Quote:
Running ...
pi1=3.141593, $sin(pi1/2)=1.000000, $cos(pi1)=-1.000000
pi2=3.141593, sin(pi2/2)=1.000000, cos(pi2)=-1.000000
... 0.015 seconds, 6.1/0.0/0.0 KBytes size/rss/shared

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Re: Math functions in Cadence NCVerilog
Reply #8 - Sep 26th, 2014, 2:31am
 
ncverilog: 08.20-s010: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
TOOL:      ncverilog      08.20-s010: Started on Sep 26, 2014 at 09:08:19 ***
ncverilog
     +nowarn+NONPRT
     +ncaccess+r
     +ncams
     -f run.f
           test.v
file: test.v
     module worklib.test:v
           errors: 0, warnings: 0
           Caching library 'worklib' ....... Done
     Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
  pi1 = $acos( -1.0);
            |
ncelab: *W,MISSYST (./test.v,5|13): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
If item was defined in a shared-object library, the problem could be:
libvpi.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS32 library.
libpli.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS32 library..
            pi1, $sin(pi1 / 2), $cos(pi1) );
                    |
ncelab: *W,MISSYST (./test.v,7|21): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
            pi1, $sin(pi1 / 2), $cos(pi1) );
                                   |
ncelab: *W,MISSYST (./test.v,7|36): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
     Building instance overlay tables: .................... Done
     Generating native compiled code:
           worklib.test:v <0x1ee5f7ce>
                 streams:   3, words:  2394
     Loading native compiled code:     .................... Done
     Building instance specific data structures.
     Design hierarchy summary:
                    Instances  Unique
           Modules:         1       1
           Registers:       2       2
           Initial blocks:  1       1
     Writing initial simulation snapshot: worklib.test:v
Loading snapshot worklib.test:v .................... Done
  pi1 = $acos( -1.0);
            |
ncsim: *E,MSSYSTF (./test.v,5|13): User Defined system task or function registered during elaboration and used within the simulation has not been registered during simulation.
            pi1, $sin(pi1 / 2), $cos(pi1) );
                    |
ncsim: *E,MSSYSTF (./test.v,7|21): User Defined system task or function registered during elaboration and used within the simulation has not been registered during simulation.
            pi1, $sin(pi1 / 2), $cos(pi1) );
                                   |
ncsim: *E,MSSYSTF (./test.v,7|36): User Defined system task or function registered during elaboration and used within the simulation has not been registered during simulation.
TOOL:      ncverilog      08.20-s010: Exiting on Sep 26, 2014 at 09:08:23 ***  (total: 00:00:04)
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boe
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Re: Math functions in Cadence NCVerilog
Reply #9 - Sep 26th, 2014, 2:37am
 
Cheap_salary,
I notice you are using NCverilog 8.20. That's a very old version. Try a current version.
- B O E
> ncverilog test.sv
ncverilog(64): 13.20-s005: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
Loading snapshot worklib.test:sv .................... Done
ncsim> source /sw/cadence/incisiv13.20.005.lnx/tools/inca/files/ncsimrc
ncsim> run
0 1 0.9999996829318346 0.0007963267107332633
Simulation complete via $finish(1) at time 0 FS + 0
./test.sv:4     $finish;
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