I am trying to test the buf key word in verilog.
The following code had been wrote. It supposed to add buffers between the input signal and output signal.
However, after the synthesize, it generates the following netlist.
What is the problem here? How to use verilog key word?
The synthesize command are
set_attribute hdl_max_memory_address_range 100000000
read_hdl -v2001 test.v
set_attribute library sage-x_tsmc_cl018g_rvt_tt_1p8v_25c.lib
write_hdl -generic test > test_syn.v
write_hdl -mapped test > test_synth_map.v
// Generated by Cadence Encounter(R) RTL Compiler RC14.22 - v14.20-s016_1
// Verification Directory fv/test
module test(in, en, out1, out2);
input in, en;
output out1, out2;
wire in, en;
wire out1, out2;
endmodule // buf