Rajdeep,

Not as far as I know (may be wrong, as synthesis (or rather the inverse of synthesis) is not really my field of expertise). It would seem rather tricky to do to me... (like turning assembly language into a high level language).

Anyway, I'd be surprised if it speeds up your mixed signal simulation. Most mixed-signal simulations have their performance limited by the analog part, not the digital part.

Regards,

Andrew.

Thanks Guys!

@Andrew: I am using AMS Designer, and this is a dc-dc converter ckt. I would have liked to write a behavioral code (that may include delay statements, as I'll be using it for simulation only) of the digital controller. I guess instead of using the schematic view of the digital ckt and using verilog view for the leaf level gates/ffs, if I use verilog view of the whole digital ckt (use gate-level netlist for the time-being) that should help speeding up the sim. And I completely agree with u that its the discrete switching signals that cross the analog-digital boundary are the main culprit....so may not be a big help!

Thanks!
Rajdeep