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Simulators >> Logic Simulators >> Gate level netlist to RTL
https://designers-guide.org/forum/YaBB.pl?num=1294668402

Message started by rajdeep on Jan 10^th, 2011, 6:06am

Title: Gate level netlist to RTL
Post by rajdeep on Jan 10^th, 2011, 6:06am

Hi folks,

Is there a tool that can generate RTL from gate level netlist? I need a behavioral code for a digital controller block (which was manually drawn). This will help me in speeding up mixed-signal simulation.

Thanks
Rajdeep

Title: Re: Gate level netlist to RTL
Post by Andrew Beckett on Jan 10^th, 2011, 10:27am

Rajdeep,

Not as far as I know (may be wrong, as synthesis (or rather the inverse of synthesis) is not really my field of expertise). It would seem rather tricky to do to me... (like turning assembly language into a high level language).

Anyway, I'd be surprised if it speeds up your mixed signal simulation. Most mixed-signal simulations have their performance limited by the analog part, not the digital part.

Regards,

Andrew.

Title: Re: Gate level netlist to RTL
Post by haykp on Jan 10^th, 2011, 11:52pm

Hi Rajdeep,

My belief is that you will not find such tool, mainly all EDA tools try to bring the design close to GDS. There will not be any tool which tries to move in reverse direction. This is my thoughts.

I believe trying to find the initial RTL may be more easy, though I am not sure that it will speed up your simulations. Also you can run the simulations with notimingcheck option, to switch of the timing checks.

Thanks,
Hayk

Title: Re: Gate level netlist to RTL
Post by rajdeep on Jan 11^th, 2011, 12:36am

Thanks Guys!

@Andrew: I am using AMS Designer, and this is a dc-dc converter ckt. I would have liked to write a behavioral code (that may include delay statements, as I'll be using it for simulation only) of the digital controller. I guess instead of using the schematic view of the digital ckt and using verilog view for the leaf level gates/ffs, if I use verilog view of the whole digital ckt (use gate-level netlist for the time-being) that should help speeding up the sim. And I completely agree with u that its the discrete switching signals that cross the analog-digital boundary are the main culprit....so may not be a big help!

Thanks!
Rajdeep

Title: Re: Gate level netlist to RTL
Post by Andrew Beckett on Jan 11^th, 2011, 2:59am

Hi Rajdeep,

Even though the digital controller is a schematic containing logic gates, it would still be simulated in the event-driven part of the simulator (assuming that the logic gates are verilog representations rather than electrical). It gets netlisted as VerilogAMS, but if there's no continuous signals, then it will remain digital. So it should be fast.

Regards,

Andrew.