mepr428
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Posts: 2
Cambridge, MA
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Hello,
I am carrying out a transient simulation in AMS but my digital block is showing unknown logical value (ULV) for various digital signals inside the block. For example, the output of an AND gate shows ULV when its inputs are clearly 1 and 0. The block is written in Verilog HDL and has been successfully simulated in ModelSim. I suspect that this could be an issue with the connect rules module but I'm not sure. I'm just wondering if anyone has encountered this problem before. Any help would be much appreciated.
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