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Unknown logical value in AMS simulation. (Read 4803 times)
mepr428
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Unknown logical value in AMS simulation.
Jul 01st, 2012, 6:02pm
 
Hello,  

I am carrying out a transient simulation in AMS but my digital block is showing unknown logical value (ULV) for various digital signals inside the block.  For example, the output of an AND gate shows ULV when its inputs are clearly 1 and 0.  The block is written in Verilog HDL and has been successfully simulated in ModelSim.  I suspect that this could be an issue with the connect rules module but I'm not sure.  I'm just wondering if anyone has encountered this problem before.  Any help would be much appreciated.
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boe
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Re: Unknown logical value in AMS simulation.
Reply #1 - Jul 3rd, 2012, 12:39pm
 
Miguel Perez,
You need to provide more information for anyone to make an educated guess... (see also http://www.designers-guide.org/Forum/guidelines.html).

- B O E
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mepr428
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Re: Unknown logical value in AMS simulation.
Reply #2 - Jul 3rd, 2012, 1:07pm
 
I have figured out the problem.  The "X" state in the logic gates was being produced because of timing specs on the connect modules.  I'll make sure to provide more details about the problem at hand next time.

Thanks.
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