On my testbench there is a digital block (dig_ABC). This digital block (dig_ABC) has many logic gates and symbol view is used
for these gates on dig_ABC level. I want to use verilog view to run the simulation for the gates.

All of the gates are in one of my libraries, but there are only symbol views and no verilog views there. The verilog views of all
of the logic gates are in a single file. I don't know how to import the verilog views to individual cells. Is it possible to just use
this single file for the gates to run the simulation?

Thank you!