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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Ring Oscillator PNOISE simulation. https://designers-guide.org/forum/YaBB.pl?num=1068532356 Message started by raymond on Nov 10th, 2003, 10:32pm |
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Title: Ring Oscillator PNOISE simulation. Post by raymond on Nov 10th, 2003, 10:32pm I am Raymond, an analog design engineer in a fabless IC design house located in Singapore. Right now I have encountered a problem in doing SpectreRF simulation, I need your guide and help. Sorry for taking your precious time. Here is my story. 0) I have a VCO project from my customer. Specification Center Frequency: 10MHz Phase Noise: -90dbc/HZ @ 60 KHz offset 1) I select the Voltage Control Ring Oscillator Type as my VCO structure. I used the PSS analysis and PNOISE analysis. Simulation condition RC extraction net list Spectre Model Noise Mode=2 The simulation result is good enough to meet the specification. Simulation result Center Frequency: 10MHz Phase Noise: -92dbc/HZ @60KHz offset 2) I taped out that VCO circuit and got the Sample. The measurement result is quite bad. Measurement result Center Frequency: 10MHz Phase Noise: -80dbc/HZ @60KHz offset So there is a big difference between the simulation result and measurement result. We had gotten a lot of help and support from Cadence Singapore. but unfortunately, we haven't figure out what's the root cause. What's my question is, 4) Is that SpectreRF PSS and PNOISE analysis suitable for the Ring Oscillator? Or PSS and PNOISE analysis is more suitable for LC type oscillator? 5) Is PNOISE result from the RC extraction net list more accurate? 6) Do we need extract the substrate (BULK) network in order to get more accurate result? 7) What's your suggestion on simulation methodology? Any special setting up is for Ring Oscillator phase noise simulation? 8) How to troubleshoot the big difference of PNOISE between the simulation result and measurement result? We assume the setting up of measurement is correct. I appreciate all of you can help! Thanks in advance!! Raymond |
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Title: Re: Ring Oscillator PNOISE simulation. Post by Paul on Nov 10th, 2003, 11:29pm Ray, did you measure the whole phase noise spectrum using a spectrum analyzer? I could imagine you should be in the 1/f3 region at 60kHz from carrier. Is the 1/f device noise modeled correctly (are the model values accurate) for your technology? If not, the simulation may not consider 1/f noise correctly, which could explain the big difference between simulation and measurement. Substrate extraction may be important if you have a noisy chip. You should be able to measure the phase noise of your VCO with everything else switched off, are you? In that case, you can suppose your substrate to be more or less quiet. Paul |
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Title: Re: Ring Oscillator PNOISE simulation. Post by raymond on Nov 11th, 2003, 12:22am Thanks! Paul, Yes, you are right. The 60Khz is in the 1/f3 region. And all other circuits were switched off when I did the measurement. So I suppose the substrate is quite. But the VCO circuit itselt contents two basic blocks, one is the bias circuit, another is the CCO(current control OSC). I got the Spectre parameter from our customer. It seems they have all those 1/f parameter. Below is my Spectre Model ..... //$*mosfet bsim3v3 noimod=2 & 3 noise parameters: + noimod=2 + noia=8.7526e+19 + noib=79484 + noic=-9.997e-13 + ef=1.06 + em=98174560 ...... 1) I was wondering the big difference between the simulation and measure result. So I add the RC extaction to my netlist to account the coupling effect between the noisy signal (CCO part) and quite signal(BIAS part). But the result from the RC extraction is still more or less same. 2) So I am wondering the power supply sharing between the BIAS circuit and CCO circuit will cause the big difference. 3) Even I am wondering the substrate coupling. Since all those published papers never mentioned the the coupling effects, power supply noise and substrate noise when they describe the phase noise in oscillator. They only theoretically analyse phase noise coming from the device noise(1/f noise, thermal noise and so on). So I confuse that for a long while. Does that means the power supply noise, coupling noise and substrate noise are not important in analysis of the phase noise of OSC? Do you have reference paper on that topic?Have you encounter same problem before? Any suggestions? Thanks for your help! Raymond |
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Title: Re: Ring Oscillator PNOISE simulation. Post by Paul on Nov 11th, 2003, 11:43pm Personally I would not bother about supply or substrate coupling if the only active blocks on chip are the bias circuit and the CCO itself. One block you may forget is the output driver. Are you using a CMOS buffer to drive the signal off chip? This might introduce a lot of supply noise. In that case, would you be able to shut it down and probe your CCO output with on-chip probing? Papers may not consider substrate and suplly noise because it is hard to analyze and depends on the other blocks yopu have on chip. The measurement results of your prototype don't correspond to what you would get in presence of a large CMOS logic chip if supply/substrate noise is an issue. For this reason many people go to differential oscillator structures to reduce supply sensitivity. Back to the noise parameters. You have the 1/f noise parameters for your devices, but what is your level of confidence. I'm always concerned about parameter confidence for flicker noise. You know, 1/f means you need to perform long measurements to see the results. Do you have any test devices on chip you could do flicker noise measurements on to confirm the parameters? Or an on-chip amplifier to measure its offset over time? Paul |
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Title: Re: Ring Oscillator PNOISE simulation. Post by dadir on Nov 25th, 2003, 4:17pm Hi raymond, I came across the problem with my chip, see my post http://www.designers-guide.com/Forum/?board=jitter;action=display;num=1064000788 What process are you using? My chip was in 0.13u technology. And also the noise model parameters that you quoted are for NMOS or PMOS. I noticed that these parameters are quite high for NMOS compared to PMOS, meaning NMOS has a lot more flicker noise than PMOS. Also, does your VCO run on regulated voltage? Is the regulator noise taken care of? What is the Kvco of your VCO? If this is high regulator noise can degrade the VCO phase noise considerably. |
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Title: Re: Ring Oscillator PNOISE simulation. Post by ethan on Jul 5th, 2005, 1:55am raymond wrote on Nov 11th, 2003, 12:22am:
Can anybody tell me where I can find these items? in which file? I could not find these items in my TSMC 0.35 mm0355v.scs (BSIM3 model file). Thanks a lot. |
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Title: Re: Ring Oscillator PNOISE simulation. Post by RANI on Feb 16th, 2011, 10:27pm raymond wrote on Nov 10th, 2003, 10:32pm:
REPECTED SIR, MYSELF DOING FINAL YEAR PROJECT ON RING VCO IN Mhz RANGE IN 0.18um CMOS Tech.. I DESIGNED THE SINGLE STAGE DELAY CELL USING PSPICE... BUT I DON'T KNOW TO PROCEED THE NEXT STEP .... BY VIEWING DIFFERENT SITES I COME TO KNOW THAT BY INCREASING THE DELAY CELLS THE FREQUENCY WILL DECREASE .... CAN YOU SAY ME HOW TO EXECUTE THE SINGLE STAGE? HEREBY I ATTACHED BY PIC OF SINGLE STAGE DELAY CELL.. THANKS IN ADVANCE BY REGARDS RANI |
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Title: Re: Ring Oscillator PNOISE simulation. Post by rfidea on Feb 16th, 2011, 11:10pm To RANI: Please stay on-topic. To Raymond: How do you measure the phase noise? With a spectrum analyser? Have you in such case in the spectrum analyser specification checked the SSB performance of it? Internally the spectrum analyser in mixing the test signal with an internal LO. You can never measure a better figure than the phase noise of that LO. Since your VCO is running at the low frequency of 10MHz maybe the spectrum analyser SSB noise is higher than expected at that frequency. |
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Title: Re: Ring Oscillator PNOISE simulation. Post by loose-electron on Feb 18th, 2011, 4:42pm You are missing a large number of things: - What is the power supply over the ring oscillator and how is it held stable? - What is the sensitivity of the ring oscillator to ground noise? - How is the output of each stage buffered and distributed? - What is the architecture of the ring oscillator? - What is the model used for stage to stage cross coupling? - What is number of delay cells used in the ring, and does the ring have the time to settle out before transitioning again? There are many many things with ring oscillators to get them right, the theory of the loop is only the starting point. Above is a brief list - then from there - - What is the foundry used, what are the models for the transistors and and are those models valid? I am guessing that you don't have real power sources (ideal voltage) contributing noise and ideal grounds as well. Also guessing that each delay cell in the ring does not settle out before transitioning again, which leads to a lot more sensitivity to environment noise as well. Most of the PLL papers published don't cover most of the important things needed to make a PLL ring oscillator run right. |
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