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Design >> Analog Design >> Metastability of comparator
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Message started by ywguo on Feb 29^th, 2004, 5:58am

Title: Metastability of comparator
Post by ywguo on Feb 29^th, 2004, 5:58am

Hello,

I am designing a comparator used in pipelined ADC. As well known, they are low resolution dynamic comparators because digital error correction can correct the offset voltage.

The comparator looks very simple. It was presented by Thomas Byunghak Cho and Paul R. Gray in 1995. The threshold voltage is determined by reference voltage and the W/L ratios of the input NMOS pair that work in linear region.

However, when I simulate, it shows obviously metastability. At the same time, in some input range it gives wrong outputs. Even though I try to change the W/L ratio of each transistos, it cannot elimante all the problems at different process, voltage, and temperature corners.

Would you like to explain the phenomemon or advise any references?

Thanks in advance!

Yawei Guo
Feb. 29, 2004

Title: Re: Metastability of comparator
Post by ywguo on Mar 8^th, 2004, 9:58pm

After trying different comparator architectures and simulator options, the comparator works well when accurate=1 is set.

The hspice manual recommends that accurate=1 should be set when simulating comparators and other high gain circuit. accurate=1 set LVLTIM=3 and DVDT=2 automatically.

Yawei Guo