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Measurements >> Phase Noise and Jitter Measurements >> To measure lock time of PLL
https://designers-guide.org/forum/YaBB.pl?num=1079298104

Message started by sachinkr on Mar 14^th, 2004, 1:01pm

Title: To measure lock time of PLL
Post by sachinkr on Mar 14^th, 2004, 1:01pm

Hi,
I am doing simulation of PLL frequency synthesizer in transient analysis using SpectreRF to find lock time and to see other signal condition. The problem is that the simualtion is taking very large time and memory. The same problem for PSS and PNoise analysis. Can anybody tell me alternative of this or any suggestion?
sachin

Title: Re: To measure lock time of PLL
Post by August West on Mar 14^th, 2004, 8:39pm

Sachin,
You haven't given us much to work with. Do you believe the simulation time is excessive? If so, why? How big is the circuit? What are the clock rates? How many time steps is it taking? What kind of machine are you using? How heavily is the machine loaded? You say it takes a lot of memory, do you mean physical memory or disk space? What tolerances are you using? Did you set the maximum time step? How many signals are you saving?

If you want help, you need to put some effort into describing the problem with sufficient detail so that someone has a chance of helping you.

-August

Title: Re: To measure lock time of PLL
Post by sachinkr on Mar 14^th, 2004, 9:22pm

Hi,
sorry for giving less information. I am working on PLL Frequency Synthesizer and i am using dual loop architecture. The operating freequency range for synthesizer is in ISM 902-926 MHz. I am using only on VCO for two loop and VCO tuning range is from 820MHz to 1 GHz with gain 28MHz/v. The input clock for first main loop is 125 KHz and for second loop 4 MHz. The second loop will set VCO frequency from 896 MHz to 926 MHz using 3-bit binary counter operating at 62.5 KHz

Title: Re: To measure lock time of PLL
Post by August West on Mar 15^th, 2004, 11:06am

If you are trying to simulate 1GHz and 67kHz signals in the same circuit at the transistor level, the simulation is going to be slow. You can try using a reduced accuracy simulator, such as UltraSim. Or you could try abstracting the simulation to a higher level using Verilog-AMS.

-August

Title: Re: To measure lock time of PLL
Post by ywguo on Jun 26^th, 2004, 11:16pm

???

But how to measure lock time in experiment? Is there anybody who could give me any reference?

Thanks

Yawei

Title: Re: To measure lock time of PLL
Post by Eugene on Jul 2^nd, 2004, 11:37am

I guess the question about measuring lock time comes down to what you have access to in the lab. Can you observe the VCO input?

As for simulation, why do you want to simulate lock time with device level models? Isn't lock time dominated by the basic functionality of the PLL blocks? The basic functionality of all blocks in the loop can be simulated much much faster with behavioral phase domain models.

Title: Re: To measure lock time of PLL
Post by Aigneryu on Jul 31^st, 2004, 1:14am

Dear ywguo,

You could find tutorials of measuring PLL setup time with kinds of instruments in the Natioanl Semiconductor Application Notes.

Hint: AN885,

You can simply use spectrum analyzer to measure setup time.
Set the span to 0Hz and maximize the video bandwidth.

Title: Re: To measure lock time of PLL
Post by Tommy on Mar 3^rd, 2005, 2:54am

Eugene wrote on Jul 2^nd, 2004, 11:37am:

Thanks Eugene,
I have been thinking on same lines. But how to proceed with a phase-domain pfd which models the initial lock up process of a PLL? The model in Ken's paper is for an (unwrapped?) phase less than 2pi. would a simple wrapping of input phase difference to the PFD work???

Thanks
Tommy

Title: Re: To measure lock time of PLL
Post by Eugene on Mar 4^th, 2005, 8:46am

If you have access to SpectreRF, I think there's an appendix in the SpectreRF user's manual called "Introduction to the PLL Library", or something like that. The appendix includes a description of a phase domain model of a 3-state PFD. There are two fundamental steps in the derivation. First, you must pull the VCO and reference integrators into the PFD model. This saves on convergence errors and makes the DC analysis of the phase domain model linearize about frequency, which is something that has a meaningful equilibrium value. More importantly, this step gives the PFD memory, which is necessary to capture the hysteretic nature of the relationship between average output and phase error. Surprisingly, this step still works for fractional N PLLs because the sigma delta noise enters the loop linearly AFTER being integrated. Thus, for fractional Ns, you also absorb the sigma delta noise integrator into the PFD too. Now the PFD has memory and can accurately simulate cycle slips, which leads to the second fundamental step. Replace the integrator with a resettable integrator. As the integrator integrates frequency error to produce phase error, it resets at +-2Pi. The appendix describes a few other tricks but these two are the key steps.

Please note that Cadence was issued a patent for the PFD model. I am fairly sure that means you can use it from within the Cadence tool set. I am not sure what it means beyond that. I have enough trouble reading technical stuff, let alone technical stuff written in legalese.

Title: Re: To measure lock time of PLL
Post by Tommy on Mar 6^th, 2005, 5:51pm

Thanks a lot Eugene for your pointers. I will pursue it.

I found the paper you were referring to on Cadence website
www.cadence.com/whitepapers/pllapp_note.pdf
I guess the ideas are public & verilog-a code is only for Cadence users :)

Thanks
Tommy

Title: Re: To measure lock time of PLL
Post by Eugene on Mar 6^th, 2005, 6:55pm

No problem. I have used the PFD many times for large and small signal analysis. Let me know if you have any questions about it.

Title: Re: To measure lock time of PLL
Post by navin_kumar on Aug 5^th, 2005, 5:28am

IIN MY VIEW IT IS BETTER TO FAST THE LOOP AND SEE THE CONTROL VOLTAGE WAVE FORM ,THEN IT MIGHT NOT TAKE THAT MUCH TIME FOR SIMULATION
AND RUN THE SIMULATION FOR 10 TIMES WHERE YOUR CONTROL VOLTAGE HAS SETTLED TO A SPECIFIED TOLLERENCE (RIPPLE) OR UR FREQUENCY OF THE VCO WITHIN THE +/- DEVIATION.