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Measurements >> Phase Noise and Jitter Measurements >> Jitter of Synchronous counters
https://designers-guide.org/forum/YaBB.pl?num=1080551252

Message started by justin on Mar 29^th, 2004, 1:07am

Title: Jitter of Synchronous counters
Post by justin on Mar 29^th, 2004, 1:07am

Hi

I am having a bit of trouble calculating the jitter of a simple clock divider. The clock divider is implemented in an Altera FPGA. The output is monitored using an Agilent Spectrum Analyzer and phase noise plotted. From there jitter is calculated by integrating. I do believe the program I have written is correct, I have compared it to answers from examples given in papers about the topic.

Quoting your document "Unlike in ripple counters, phase noise does not accumulate with each stage in synchronous counters"

I agree with the above but the test results tell me otherwise:

Output frequency Jitter
100 Mhz 12 ps
25 Mhz 23 ps
6.25 Mhz 98 ps

I would think the jitter would stay more or less the same as output frequency decreases.

Does any one have any ideas as to what is happening here ?

Cheers

Title: Re: Jitter of Synchronous counters
Post by Jitter Man on Mar 29^th, 2004, 7:25pm

If you just connect a spectrum analyzer to the output of a divider, you are seeing the noise produced by the output "at all time", which includes the noise produced while it is sitting high or sitting low. This noise does not contribute to jitter. This is explained more fully in sections 35 and 36 in http://www.designers-guide.com/Theory/cyclo-preso.pdf.

I suspect that you are going to have to use a time-interval analyzer rather than a spectrum analyzer.

[glb]Jitter Man[/glb]

Title: Re: Jitter of Synchronous counters
Post by Aigneryu on Jul 31^st, 2004, 1:18am

Dear justin

You can also use Communications system analyzer to directly measure jitters.