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Simulators >> Circuit Simulators >> About PSS & Pnoise analysis in SpectreRF
https://designers-guide.org/forum/YaBB.pl?num=1081323882

Message started by VincentLee on Apr 7^th, 2004, 12:44am

Title: About PSS & Pnoise analysis in SpectreRF
Post by VincentLee on Apr 7^th, 2004, 12:44am

Hello everyone,
I have tried to simulate the phase noise(PN) in SpectreRF because of the PSS & Pnoise analysis. However, the PSS analysis can not be convergence well. So I wonder if Hspice can do the same function as PSS & Pnoise in SpectreRF.
Firstly, I think the PLL circuit can obtain the steady state after a long time by tran analysis. And then I can save many operating points in a period wave. Just like the PSS analysis in SpectreRF.
Secondly, I can use these OP values to do noise analysis. But at this time, a problem occurs: How to consider this?
"Active elements with a time-varying bias point can convert noise from one frequency to another, a process known as noise folding, regardless of the origin of the noise."
Reference in the manual "Periodic S-parameter and noise analysis using SpectreRF PSP/PNOISE analyses"
Who know how to consider the noise folding effect in Hspice?
Thanks & Best Regards
Vincent Lee

Title: Re: About PSS & Pnoise analysis in SpectreRF
Post by Ken Kundert on Apr 7^th, 2004, 10:38am

A periodic noise analysis is not possible to perform in HSpice. Those noise analyses at each operating point are not independent, they are all linked. That is how PNoise can predict noise in switched-capacitor filters. In SC filters there is no point in time where there is a direct path from input to output, thus with the independent noise analyses the noise at the input would never make it to the output.

You should focus on getting convergence with PSS. If you just run a long tstab with default tolerances, you should be fine as long as your PLL has a periodic steady state.

-Ken

Title: Re: About PSS & Pnoise analysis in SpectreRF
Post by Andrew Beckett on Apr 7^th, 2004, 12:53pm

Also, as you say you are trying to simulate a PLL, you should
read Ken's paper:

http://www.designers-guide.com/Analysis/PLLnoise+jitter.pdf

which goes into this in some detail. I suspect that you may
be trying to simulate the whole PLL in one go, which is often tricky... (see the paper for more info).

Regards,

Andrew.