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Design >> Analog Design >> Suggest me the architecture of Ring VCO!
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Message started by VincentLee on Apr 28^th, 2004, 1:05am

Title: Suggest me the architecture of Ring VCO!
Post by VincentLee on Apr 28^th, 2004, 1:05am

Hello everyone,

I am designing a VCO in a PLL which uses for clock generator in MCU. So its operating frequency is not very high, tuning range is about 10MHz~200MHz. And it will be implemented by CMOS 0.6um process with 5V power supply. In addition, the input control voltage also needs wide control range.

In many specs, I focus on the lower phase noise characteristics and higher PSRR. Firstly, due to the low frequency application, I select the Ring VCO. However, there are so lots of IEEE papers about the Ring VCO that I can't decide which one is best for me.

So please suggest me the achitecture of Ring VCO! I would like use the differential cascode structure to build my Ring VCO, how do you think about its performence?
Thanks in advance!

Best Regards,
Vincent

Title: Re: Suggest me the architecture of Ring VCO!
Post by Augustine B Lytan on Apr 29^th, 2004, 11:21am

Hi,
The delay with balanced loads by maneatis is one of the most popular one as it has very good psrr. you can have a look at the paper:
Low-jitter Process-Independent DLL and PLL Based on Self-Bias Techniques

Author: John G. Maneatis
IEEE Journal of Solid-state circuits, Vol 31, No 11, November 1996.

Hope this helps.
Regards,
augustine.