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Measurements >> Phase Noise and Jitter Measurements >> design strategy to minimize cycle to cycle jitter
https://designers-guide.org/forum/YaBB.pl?num=1088993465

Message started by busywind on Jul 4^th, 2004, 7:11pm

Title: design strategy to minimize cycle to cycle jitter
Post by busywind on Jul 4^th, 2004, 7:11pm

Hi Everybody,

I can find a lot research work about how to minimize the RMS jitter for a PLL. I have been thinking about some questions such as what's the general design strategy to minimize the cycle to cycle jitter for a PLL, what's the relationship between phase noise and cycle to cycle jitter etc. Can somebody give me some hints or recommend some papers for me to read?

Many thanks,

Busywind

Title: Re: design strategy to minimize cycle to cycle jit
Post by ywguo on Jul 11^th, 2004, 9:43am

Sorry, busywind,

I don't know the answer, too. But I want to discuss the measurement of cycle-to-cycle jitter. Do you know how to measure the cycle-to-cycle jitter?

Thanks

Yawei

Title: Re: design strategy to minimize cycle to cycle jit
Post by busywind on Jul 11^th, 2004, 7:01pm

Yawei,

Basically, there are two methods to measure cycle to cycle jitter. The first one is to use a timing interval analyzer and the second one is to use a scope and a timing interval analyzing software (for example, Wavecrest SIA-300 and JIT3 etc). The concept of measuring cycle to cycle jitter is simple but it requires that the equipements must be accurate and precise.

Busywind.

Title: Re: design strategy to minimize cycle to cycle jit
Post by ywguo on Jul 24^th, 2004, 5:07am

Hi, Busywind,

Which company does JIT3 belong to?

By the way, is there any method to measure cycle-to-cycle jitter using digital osciliscope? I have a Tektronix TDS5052 Phosphor Digital Osciliscope.

Thanks

Yawei